624
SB-RMI
Processor
State
Accesses
May
Persistently
Timeout
if
Interrupted
by
a
Warm
Reset
Description
The
assertion
of
a
warm
reset
during
a
small
timing
window
of
an
APML
SB-RMI
processor
state
access
may
cause
the
internal
processor
state
access
interface
to
hang
.
A
protocol
status
code
of
11
h
or
12
h
(
Command
Timeout
)
is
returned
,
however
,
the
internal
interface
remains
hung
and
all
future
SB-RMI
processor
state
accesses
receive
command
timeouts
until
a
cold
reset
is
performed
.
If
SB-RMI
timeouts
are
disabled
(
Control
Register
[
TimeoutDis
],
SBRMI
_
x
01[2]),
the
SB-RMI
processor
state
accesses
will
not
receive
a
successful
completion
,
instead
of
a
command
timeout
.
Potential
Effect
on
System
Under
rare
circumstances
,
system
management
software
will
not
be
able
to
access
processor
state
using
SB-RMI
processor
state
accesses
.
SB-TSI
accesses
and
SB-RMI
register
accesses
are
not
impacted
.
Refer
to
Advanced
Platform
Management
Link
(
APML
)
Specification
,
order
# 41918
for
details
on
differentiating
SB-RMI
processor
state
accesses
from
SB-
RMI
register
accesses
.
Suggested
Workaround
None
required
.
Fix
Planned
Yes
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
48063
Rev
. 3.18
October
2012
44
Product
Errata