717
Instruction-Based
Sampling
May
Be
Inaccurate
Description
The
processor
may
experience
sampling
inaccuracies
when
Instruction-Based
Sampling
(
IBS
)
is
enabled
in
the
following
cases
:
•
When
IBS
Op
Data
3
Register
[
IbsDcMiss
] (
MSRC
001_1037[7])
is
0
b
,
IBS
Op
Data
3
Register
[
IbsDcMabHit
] (
MSRC
001_1037[16])]
should
always
be
0
b
.
However
,
the
processor
may
incorrectly
set
IbsDcMabHit
.
•
When
the
processor
samples
an
instruction
that
is
altering
the
CS
_
BASE
value
,
the
IbsOpRip
reported
in
IBS
Op
Logical
Address
(
MSRC
001_1034)
may
be
determined
using
an
incorrect
CS
_
BASE
.
•
In
rare
instances
,
a
tagged
branch
may
set
an
inaccurate
value
in
IBS
Branch
Target
Address
Register
(
MSRC
001_103
B
).
Potential
Effect
on
System
Inaccuracies
in
performance
monitoring
software
may
be
experienced
.
Suggested
Workaround
The
following
workarounds
can
be
used
for
the
above
issues
:
•
Performance
monitoring
software
should
treat
IBS
Op
Data
3
Register
[
IbsDcMabHit
] (
MSRC
001_1037[16])
as
0
b
when
MSRC
001_1037[7]
is
0
b
.
•
No
workaround
is
necessary
for
IbsOpRip
when
CS
_
BASE
is
zero
.
CS
_
BASE
is
normally
zero
in
commercially
available
software
.
•
Performance
monitoring
software
should
not
rely
on
the
value
in
MSRC
001_103
B
(
IbsBrTarget
).
Fix
Planned
Yes
48063
Rev
. 3.18
October
2012
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
Product
Errata
75