699
Processor
May
Generate
Illegal
Access
in
VMLOAD
or
VMSAVE
Instruction
Description
The
processor
may
generate
a
speculative
access
during
execution
of
a
VMLOAD
or
VMSAVE
instruction
.
The
memory
type
used
for
this
access
is
defaulted
to
WB
DRAM
memory
type
,
however
the
address
used
may
not
be
a
valid
DRAM
address
or
it
may
be
an
address
that
is
not
specified
as
cacheable
in
the
memory
type
(
i
.
e
.,
the
actual
memory
type
is
UC
or
WC
).
Potential
Effect
on
System
When
the
address
is
not
a
valid
DRAM
address
,
the
processor
may
recognize
a
northbridge
machine
check
exception
for
a
link
protocol
error
.
This
machine
check
exception
causes
a
sync
flood
and
system
reset
under
AMD
recommended
BIOS
settings
.
The
machine
check
has
the
following
signature
:
•
The
MC
4_
STAT
register
(
MSR
0000_0411)
is
equal
to
BA
000020_000
B
0
C
0
F
.
Bit
62 (
error
overflow
)
or
bit
59 (
miscellaneous
valid
)
of
MC
4_
STAT
may
or
may
not
be
set
.
•
Bits
5:1
of
the
MC
4_
ADDR
register
(
MSR
0000_0412)
is
equal
to
01001
b
,
indicating
that
a
coherent-only
packet
was
issued
to
a
non-coherent
link
.
When
the
address
is
actually
a
non-cacheable
memory
type
,
the
processor
may
incorrectly
cache
the
data
,
resulting
in
unpredictable
system
behavior
.
AMD
has
only
observed
a
northbridge
link
protocol
error
machine
check
.
The
incorrect
caching
of
an
uncacheable
memory
region
has
not
been
observed
by
AMD
.
Suggested
Workaround
Contact
your
AMD
representative
for
information
on
a
BIOS
update
.
Fix
Planned
No
fix
planned
48063
Rev
. 3.18
October
2012
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
Product
Errata
69