593
Last-Branch
Record
Enabled
May
Cause
Machine
Check
and
Incorrect
LastBranchToIp
Description
When
LBR
is
enabled
,
a
complex
interaction
between
two
threads
of
the
same
compute-unit
may
result
in
the
processor
core
reporting
an
incorrect
value
in
the
LastBranchToIp
register
(
MSR
0000_01
DC
).
Potential
Effect
on
System
In
rare
circumstances
,
the
value
reported
in
LastBranchToIP
may
present
incorrect
debug
information
.
The
processor
may
also
report
an
uncorrectable
machine
check
exception
for
a
branch
status
register
parity
error
,
simultaneous
to
the
above
error
.
MC
1_
STATUS
[
ErrorCodeExt
] (
MSR
0000_0405[20:16]) = 00110
b
identifies
a
branch
status
register
parity
error
.
Suggested
Workaround
BIOS
should
set
MSRC
001_0045[15] = 1
b
(
MC
1_
CTL
_
MASK
[
BSRP
]).
This
workaround
does
not
resolve
the
potential
for
an
incorrect
address
to
be
provided
in
LastBranchToIp
.
This
latter
effect
has
negligible
impact
on
debugging
due
to
the
low
probability
of
the
error
occurring
when
this
data
is
being
collected
.
No
workaround
is
required
for
this
aspect
.
Fix
Planned
Yes
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
48063
Rev
. 3.18
October
2012
38
Product
Errata