695
Processor
May
Interpret
FCW
Incorrectly
after
FNSAVE
/
FSAVE
Limit
Fault
Description
The
processor
operates
as
if
the
floating-point
control
word
(
FCW
)
has
been
initialized
after
executing
an
FNSAVE
or
FSAVE
instruction
which
generates
a
stack
limit
fault
(
SS
).
This
occurs
when
the
instruction
attempts
to
store
the
state
of
the
floating-point
unit
to
a
memory
location
that
crosses
a
16
-bit
(0
xFFFF
)
or
32
-bit
(0
xFFFF
_
FFFF
)
address
boundary
in
real
or
protected
mode
respectively
,
and
persists
until
software
reinitializes
the
FCW
.
The
FXSAVE
instruction
is
not
affected
by
this
erratum
.
Potential
Effect
on
System
None
expected
during
normal
operation
.
A
stack
limit
fault
while
executing
an
FNSAVE
or
FSAVE
instruction
is
unusual
and
AMD
has
not
observed
the
above
conditions
in
any
commercially
available
software
.
In
the
unlikely
event
that
software
creates
the
conditions
described
above
one
of
the
following
may
occur
:
•
The
processor
may
write
an
indefinite
value
,
as
if
masked
,
when
signaling
an
invalid-operation
exception
(
IE
)
after
an
FLD
instruction
executes
with
invalid
operands
while
invalid
operations
are
unmasked
(
FCW
.
IM
,
bit
0 = 0
b
).
•
The
processor
may
set
the
FERR
signal
incorrectly
after
an
FLDCW
instruction
updates
the
floating-point
control
word
mask
bits
(
FCW
[5:0]).
A
subsequent
floating
point
operation
may
then
result
in
an
incorrect
or
missing
x
87
floating-point
exception
(#
MF
).
Suggested
Workaround
None
required
.
Fix
Planned
No
fix
planned
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
48063
Rev
. 3.18
October
2012
68
Product
Errata