759
One
Core
May
Observe
a
Time
Stamp
Counter
Skew
Description
During
a
P-state
change
or
following
a
C-state
change
,
the
processor
core
may
synchronize
an
internal
copy
of
the
time
stamp
counter
(
TSC
)
incorrectly
.
The
processor
may
then
observe TSC values (e.g., RDTSC, R
DTSCP
and
RDMSR
0000_0010
h
instructions
)
or
MPERF
(
MSR
0000_000
E
7)
values
that
do
not
account
for
the
time
spent
performing
this
last
P-state
or
C-state
change
.
This
error
is
normally
temporary
in
nature
,
in
that
it
may
be
resolved
after
the
next
P-state
or
C-state
change
.
Potential
Effect
on
System
System
software
or
software
with
multiple
threads
may
observe
that
one
thread
or
processor
core
provides
TSC
values
that
are
behind
all
of
the
other
threads
or
processor
cores
.
While
a
single
thread
operating
on
a
single
core
can
not
observe
successively
stored
TSC
values
that
incorrectly
decrement
,
it
is
possible
that
a
single
thread
may
be
dispatched
on
one
core
,
where
the
software
observes
a
TSC
,
and
is
then
dispatched
by
the
operating
system
on
another
core
that
has
encountered
the
conditions
of
the
erratum
.
In
this
sequence
of
events
,
the
thread
may
observe
a
TSC
that
appears
to
decrement
.
In
addition
,
software
may
calculate
a
higher
effective
frequency
(
APERF
,
MSR
0000_00
E
8,
divided
by
MPERF
).
Suggested
Workaround
Contact
your
AMD
representative
for
information
on
a
BIOS
update
.
Fix
Planned
Yes
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
48063
Rev
. 3.18
October
2012
90
Product
Errata