Operating
System
Visible
Workarounds
This
section
describes
how
to
identify
operating
system
visible
workarounds
.
MSRC
001_0140
OS
Visible
Work-around
MSR
0 (
OSVW
_
ID
_
Length
)
This
register
,
as
defined
in
AMD
64
Architecture
Programmer's
Manual
Volume
2:
System
Programming
,
order
#
24593,
is
used
to
specify
the
number
of
valid
status
bits
within
the
OS
Visible
Work-around
status
registers
.
The
reset
default
value
of
this
register
is
0000_0000_0000_0000
h
.
BIOS
shall
program
the
OSVW
_
ID
_
Length
to
0005
h
prior
to
hand-off
to
the
OS
.
Bits
Description
63:16
Reserved
.
15:0
OSVW
_
ID
_
Length
:
OS
visible
work-around
ID
length
.
Read-write
.
MSRC
001_0141
OS
Visible
Work-around
MSR
1 (
OSVW
_
Status
)
This
register
,
as
defined
in
AMD
64
Architecture
Programmer's
Manual
Volume
2:
System
Programming
,
order
#
24593,
provides
the
status
of
the
known
OS
visible
errata
.
Known
errata
are
assigned
an
OSVW
_
ID
corresponding
to
the
bit
position
within
the
valid
status
field
.
Operating
system
software
should
use
MSRC
001_0140
to
determine
the
valid
length
of
the
bit
status
field
.
For
all
valid
status
bits
: 1=
Hardware
contains
the
erratum
,
and
an
OS
software
work-around
is
required
or
may
be
applied
instead
of
a
BIOS
workaround
. 0=
Hardware
has
corrected
the
erratum
,
so
an
OS
software
work-around
is
not
necessary
.
The
reset
default
value
of
this
register
is
0000_0000_0000_0000
h
.
Bits
Description
63:5
OsvwStatusBits
:
Reserved
.
OS
visible
work-around
status
bits
.
Read-write
.
4
OsvwId
4: 1 =
Hardware
contains
erratum
#724
,
an
OS
workaround
may
be
applied
if
available
; 0 =
Hardware
has
corrected
erratum
#724
.
3
OsvwId
3:
Reserved
,
must
be
zero
..
2
OsvwId
2:
Reserved
,
must
be
zero
..
1
OsvwId
1:
Reserved
,
must
be
zero
..
0
OsvwId
0:
Reserved
,
must
be
zero
..
BIOS
shall
program
the
state
of
the
valid
status
bits
as
shown
in
Table
6
prior
to
hand-off
to
the
OS
.
Table
6.
Cross
Reference
of
Product
Revision
to
OSVW
ID
CPUID
Fn
0000_0001_
EAX
(
Mnemonic
)
MSRC
001_0141
Bits
00600
F
12
h
(
OR-B
2)
0000_0000_0000_0010
h
00600
F
20
h
(
OR-C
0)
0000_0000_0000_0010
h
48063
Rev
. 3.18
October
2012
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
Operating
System
Visible
Workarounds
13