720
Processor
May
Not
Respect
Interrupt
Shadow
Description
Under
a
highly
specific
and
detailed
set
of
internal
timing
conditions
,
a
#
DB
exception
may
be
presented
during
execution
of
an
instruction
that
is
in
an
interrupt
shadow
.
In
order
for
this
erratum
to
occur
,
the
other
processor
core
in
the
compute-unit
must
be
performing
microcoded
functions
that
are
uncommon
in
usage
.
Potential
Effect
on
System
Under
rare
circumstances
,
a
debug
exception
may
occur
in
an
interrupt
shadow
.
Under
common
software
use
,
this
exception
does
not
have
a
system
effect
.
In
the
event
that
system
software
uses
"STI
,
RET"
instead
of
a
single
IRET
instruction
,
or
changes
the
stack
segment
simultaneously
with
the
stack
pointer
(
i
.
e
.
not
using
a
flat
segment
for
the
stack
),
unpredictable
system
failure
may
result
.
AMD
has
not
observed
this
erratum
with
any
commercially
available
software
.
Suggested
Workaround
None
.
Fix
Planned
No
fix
planned
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
48063
Rev
. 3.18
October
2012
78
Product
Errata