708
Initial
Value
of
Time
Stamp
Counter
May
Include
an
Offset
Error
Description
During
the
interval
of
time
between
the
northbridge
observing
the
RESET
#
deassertion
and
the
processor
cores
initializing
internal
copies
of
the
time
stamp
counter
(
TSC
),
the
TSC
appears
to
increment
at
a
rate
that
is
twice
the
actual
processor
core
software
P
0
frequency
.
This
introduces
an
initial
offset
error
in
the
reset
value
for
each
processor
core
.
The
actual
value
of
the
offset
error
is
unpredictable
.
On
the
first
case
of
any
P-state
change
(
either
due
to
a
P-state
limit
change
or
a
software
initiated
P-state
change
),
any
halt
instruction
or
C-state
activity
,
the
above
initial
offset
error
is
removed
.
It
is
possible
that
the
BIOS
could
observe
the
TSC
to
change
to
a
smaller
value
(
i
.
e
.,
the
TSC
may
appear
to
decrement
once
)
if
the
latency
of
this
operation
is
less
than
the
above
introduced
error
.
If
the
software
was
to
perform
a
write
to
the
TSC
before
this
event
,
the
offset
error
is
also
removed
.
Potential
Effect
on
System
None
expected
under
normal
circumstances
.
Suggested
Workaround
Contact
your
AMD
representative
for
information
on
a
BIOS
update
.
Fix
Planned
No
fix
planned
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
48063
Rev
. 3.18
October
2012
72
Product
Errata