MC96FR116C
November, 2018 Rev.1.8
71
11.1.3 Register Map
Name
Address
Dir
Default
Description
SCCR
8A
H
R/W
00
H
System and Clock Control Register
MCCR
EF
H
R/W
33
H
Main Oscillator Clock Control Register
Table 11-1 Register Map of Clock Generator
11.1.4 Register Description
SCCR (System and Clock Control Register)
8A
H
7
6
5
4
3
2
1
0
ROSCEN
DIV1
DIV0
BCLKS
MOSCEN
IOSCEN
-
CLKSEL
R/W
R/W-
R/W
R/W-
R/W
R/W-
-
R/W
Initial value : 64
H
ROSCEN
The operation of RING Oscillation at stop mode.
0
Ring-Oscillator is disabled at stop mode.
1
Ring-Oscillator is enabled at stop mode.
DIV[1:0]
Selects the divide ratio of operating clock sources, XIN and INT-
RC.
DIV1
DIV0
Description (in case of f
INT-RC
=12MHz)
0
0
f
INT-RC
/1 (12MHz)
0
1
f
INT-RC
/1.5 (8MHz)
1
0
f
INT-RC
/2 (6MHz)
1
1
f
INT-RC
/3 (4MHz)
BCLKS
BIT clock source selection
0
BIT clock source is system clock.
1
BIT clock source is internal RING oscillator.
MOSCEN
Main oscillator enable
0
Main oscillator is disable.
1
Main oscillator is enable.
IOSCEN
Internal oscillator enable
0
Internal RC oscillator is disable.
1
Internal RC oscillator is enable.
CLKSEL
System clock source selection
0
Internal RC oscillator is system clock source.
1
Main oscillator is system clock source.
