Abov MC96FR116C Series, User Manual

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MC96FR116C
64 November, 2018 Rev.1.8
EIPS2 2F1A
H
R/W 02
H
External Interrupt Port Select 2 Register
EIPS3 2F1B
H
R/W 03
H
External Interrupt Port Select 3 Register
EIPS4 2F1C
H
R/W 04
H
External Interrupt Port Select 4 Register
EIPS5 2F1D
H
R/W 05
H
External Interrupt Port Select 5 Register
Table 10-3 Register Map of Interrupt Controller
10.12.2 Interrupt Enable Register (IE, IE1, IE2, IE3)
There
’re 4 interrupt enable registers which are IE, IE1, IE2 and IE3. In IE register, there’s two kinds of
interrupt enable bits called the global interrupt enable bit, EA, and 6 individual interrupt enable bits,
INTnE. Each IE1, IE2 and IE3 register only has 6 individual interrupt enable bits. Totally 16 peripheral
and external interrupts are controlled by these registers.
10.12.3 Interrupt Priority Register (IP, IP1)
As described above, each interrupt enable register has 6 individual interrupt enable bits. So, interrupt
controller itself can deal up to 24 interrupt sources. These 24 sources are classified into 6 groups by 4
sources. Each group can have 4 level of priority through IP and IP1 registers. The level 3 group
interrupt is of the highest priority, and the level 0 group interrupt is of the lowest priority. The initial
values of IP and IP1 registers are 00
H
. By default, the lower numbered interrupt has the higher priority
if group priority is the same. When the group priority is decided by configuring IP and IP1 registers,
among 4 interrupt sources within the group, the lower numbered interrupt has the higher priority.
10.12.4 External Interrupt Flag Register (EIFLAG)
External Interrupt Flag Register shows the status of external interrupts. Each flag is set to
‘1’ when a
port is configured as an external interrupt source, and the port state changes to equal to the interrupt
generating condition according to EIEDGEx and EIPOLA register. To clear each flag, write
‘0’ to
corresponding bit position of this register.
10.12.5 External Interrupt Edge Register (EIEDGEx)
External Interrupt Edge Register decides the trigger mode of external interrupt, edge or level mode.
To make an external interrupt triggered by a falling or rising edge, write
‘00
B
’ to the corresponding bit
position. And to make an external interrupt triggered by a low or high level, write
‘01
B
’, ‘10
B
’ or ‘11
B
’ to
the corresponding bit position. Initially, all external interrupts are triggered by high level. Note there
are 2 bits for each external interrupt pin.
10.12.6 External Interrupt Enable Register (EIENAB)
External Interrupt Enable Register selects each port pin, which has sub function for external interrupt,
whether to use as external interrupt pin or normal port pin. When a bit in this register is written
‘0’, the
corresponding pin is used as general purpose I/O pin.
10.12.7 External Interrupt Port Selection x Register (EIPSx)
External Interrupt Port Selection x Register selects each port pin with external interrupt source.