MC96FR116C
72
November, 2018 Rev.1.8
MCCR (Main Oscillator Clock Control Register)
EF
H
7
6
5
4
3
2
1
0
-
-
ISELM1
ISELM0
-
-
ISEL1
ISEL0
-
-
R
R
-
-
R/W
R/W
Initial value : 33
H
ISELM[1:0]
Monitors the current strength of main oscillator. ISELM is updated
with ISEL at the MOSCEN of SCCR is 0 or STOP mode.
ISELM1
ISELM1
Description
0
0
X1
0
1
X2
1
0
X3
1
1
X4
ISEL[1:0]
Selects the current strength of main oscillator. The applied time is
not ISEL, but ISELM.
ISEL1
ISEL1
Description
0
0
X1
0
1
X2
1
0
X3
1
1
X4
11.2 Basic Interval Timer (BIT)
11.2.1 Overview
BIT module is a 8-bit counter used to guarantee oscillator stabilization time when MC96FR116C is
reset or waken from STOP mode. The BIT counter is clocked by a clock divided from system
clock(SCLK) and the divide ratio is selected from BCK[2:0] bits in BCCR register, from 16 to 2048. At
reset, the BIT counter is clocked by a clock which is divided by 512 from SCLK. If BCLKS of SCCR is
set, BIT counter is clocked by a clock which is divided by 1024 from RING oscillator, regardless of
BCK[2:0].
BIT is a 8-bit binary counter and has the following features.
-
Guarantees the oscillation stabilization time when a power-on or reset occurs
-
Guarantees the oscillation stabilization time when this device wakes-from STOP mode
-
Generates interval timer interrupt as a watch function
