MC96FR116C
76
November, 2018 Rev.1.8
11.3.3 Register Map
Name
Address
Dir
Default
Description
WDTR
8E
H
W
FF
H
Watch Dog Timer Register
WDTCR
8E
H
R
00
H
Watch Dog Timer Counter Register
WDTMR
8D
H
R/W
00
H
Watch Dog Timer Mode Register
Table 11-3 Register Map of WDT
11.3.4 WDT Interrupt Timing
Source Clock
BIT Overflow
WDTCR[7:0]
WDTR[7:0]
WDTIF
Interrupt
WDTRESETB
WDTCL
Occur
WDTR
0000_0011b
Match
Detect
Counter Clear
RESET
0
1
2
3
0
1
2
3
0
1
2
n
3
Figure 11-4 WDT Interrupt and Reset Timing
