MC96FR116C
November, 2018 Rev.1.8
109
-
-
W
W
W
W
W
W
Initial value : 3F
H
WTDR[13:8]
Select WT overflow period. Reading this register returns the high
8-bit WTIR counter value.
WT Interrupt Interval = (Twck x 2^14) x (7-bit WTDRH) + (Twck x
14-bit WTDR)
WTDR0 (Watch Timer Data Register 0)
D5
H
7
6
5
4
3
2
1
0
WTDR7
WTDR6
WTDR5
WTDR4
WTDR3
WTDR2
WTDR1
WTDR0
W
W
W
W
W
W
W
W
Initial value : FF
H
WTDR[7:0]
Select WT overflow period. Reading this register returns the low 8-
bit WTIR counter value.
WTSR (Watch Timer Status Register)
D9
H
7
6
5
4
3
2
1
0
IRI
-
-
-
-
-
-
WTIFR
R
-
-
-
-
-
-
R
Initial value : 00
H
IRI
IRI status (IRAMP output or Port input)
0
IRI is ‘0’
1
IRI is ‘1’
WTIFR
Interrupt flag of WT. This flag bit is cleared when the interrupt is
serviced or by writing ‘0’ to this bit field.
0
No WT interrupt is generated
1
WT interrupt occurred
WTDRH (Watch Timer Data Register High)
DC
H
7
6
5
4
3
2
1
0
-
WTDRH6
WTDRH5
WTDRH4
WTDRH3
WTDRH2
WTDRH1
WTDRH0
-
W
W
W
W
W
W
W
Initial value : 7F
H
WTDRH[6:0]
Select WT overflow period. Reading this register returns WT_TMR
counter value, the high 7-bit counter.
WTCR0H (Watch Timer Capture Register 0 High)
F1
H
7
6
5
4
3
2
1
0
-
-
WTCR013
WTCR012
WTCR011
WTCR010
WTCR009
WTCR008
-
-
R
R
R
R
R
R
Initial value : 3F
H
WTCR0[13:8]
When WT is in IR capture mode, the high 6-bit of WTIR counter is
captured to this register at the first falling edge (when PHASE bit is
‘0’) or first rising edge (when PHASE bit is ‘1’) of input carrier
signal. This register is initialized
by setting WTCL bit in WTMR.
