MC96FR116C
November, 2018 Rev.1.8
75
11.3 Watch Dog Timer (WDT)
11.3.1 Overview
The WDT, if enabled, generates an interrupt or a system reset when the WDT counter reaches the
given time-out value set in WDTR. In normal operation mode, it is required that the user software
clears the WDT counter by setting WDTCL bit in WDTMR register before the time-out value is
reached. If the system doesn
’t restart the counter, an interrupt or a system reset will be issued.
The main features are :
-
2 operating modes : Interrupt or System Reset mode
-
Selectable Time-out period
In Interrupt mode, the WDT gives an interrupt when the WDT counter expires. This interrupt can be
used to wake the device from SLEEP mode (not from STOP mode
NOTE
), and also as a general
system timer. One example is to limit the maximum time allowed for certain operations, giving an
interrupt when the operation has run longer than expected. In System Reset mode, the WDT gives a
reset when the timer expires. This is typically used to prevent system hang-up in case of runaway
code.
The clock source of Watch Dog Timer is the BIT overflow. The interval of WDT interrupt is decided by
BIT overflow period and WDTR value, and is calculated as follows.
WDT Interrupt Interval = (BIT overflow period) x (WDTR + 1)
NOTE
MC96FR116C has only one clock source, XINCLK, and in STOP mode, the main oscillator stops. Also, the
WDT/BIT module stops operation.
11.3.2 Block Diagram
Figure 11-3 Block Diagram
To Reset
Circuit
[
8E
H
]
Clear
WDTEN
BIT Overflow
WDTCR
WDTR
Watchdog Timer
Register
[8E
H
]
Watchdog Timer
Counter Register
WDTIFR
WDTMR
WDTCL
WDTRSON
INT_ACK
Clear
WDTIF
