Abov MC96FR116C Series, User Manual

Page: 63 / 196

MC96FR116C
November, 2018 Rev.1.8 63
10.11 Interrupt Timing
The interrupt request is sampled at the last cycle of the command currently being executed. On
recognition of interrupt request, the interrupt controller hands over the corresponding lower 8-bit
vector address to the CPU, M8051W and the CPU acknowledges the request at the first cycle of the
next command to jump to the interrupt vector address.
NOTE
command cycle C?P? : L=Last cycle, 1=1
st
cycle or 1
st
phase, 2=2
nd
cycle or 2
nd
phase
10.12 Interrupt Registers
10.12.1 Register Map
Name Address Dir Default Description
IE A8
H
R/W 00
H
Interrupt Enable Register
IE1 A9
H
R/W 00
H
Interrupt Enable Register 1
IE2 AA
H
R/W 00
H
Interrupt Enable Register 2
IE3 AB
H
R/W 00
H
Interrupt Enable Register 3
IP B8
H
R/W 00
H
Interrupt Priority Register
IP1 F8
H
R/W 00
H
Interrupt Priority Register 1
EIFLAG AC
H
R/W 00
H
External Interrupt Flag Register
EIEDGE0 AD
H
R/W 00
H
External Interrupt Edge0 Register
EIEDGE1 AE
H
R/W 00
H
External Interrupt Edge1 Register
EIENAB B1
H
R/W 00
H
External Interrupt Enable Register
EIPS0 2F18
H
R/W 00
H
External Interrupt Port Select 0 Register
EIPS1 2F19
H
R/W 01
H
External Interrupt Port Select 1 Register
CLP2 CLP1 C2P1 C1P1 C2P2 C1P2 CLP2
Interrupt sampled here
8-bit interrupt Vector
INT_SRC
INTR_ACK
LAST_CYC
INTR_LCALL
INT_VEC
PROGA
SCLK
{8
’h00, INT_VEC}
NOTE
Figure 10-9 Timing chart for Interrupt Accept and Branch Address Generation