MC96FR116C
November, 2018 Rev.1.8
49
9. I/O PORTS
9.1 Introduction
The MC96FR116C has four I/O ports (P0, P1). Each port can be easily configured by software
whether to use internal pull up resistor or not, whether to use open drain output or not, or whether the
pin is input or output. Also P0 includes function that can generate interrupt when the state of P0
changes.
9.2 Register Description
9.2.1 Data Register (Px)
Data Register is a bidirectional I/O port. If ports are configured as output ports, data can be written to
the corresponding bit in the Px. If ports are configured as input ports, the port value can be read from
the corresponding bit in the Px.
9.2.2 Direction Register (PxIO)
The PxnIO bit in the PxIO register selects the direction of this pin. If PxnIO is written logic one, Pxn is
configured as an output pin. If PxnIO is written logic zero, Pxn is configured as an input pin. All bits
are cleared by a system reset.
9.2.3 Pull-up Resistor Selection Register (PxPU)
All ports P0, P1 have optional internal pull-ups. The PxnPU bit in the PxPU register allows the use of
pull-up resistor. If PxnPU is written logic one, the pull-up resistor is activated. If PxnPU is written logic
zero, the pull-up resistor is deactivated. When the port is configured as an input port, internal pull-up
is deactivated regardless of the PxnPU bit. After reset, all pull-up resistors are switched off except
those of P1[2]. According to PKG types, some of these ports are omitted, so to maintain input status,
the internal pull-ups for these ports are activated.
9.2.4 Open-drain Selection Register (PxOD)
The PxnOD bit in the PxOD register controls the port type when configured as an output port. If
PxnOD is written logic one, the port becomes open-drain type. If PxnOD is written logic zero, the port
becomes push-pull type. After reset, open-drain function is disabled.
Caution
: Port 0 has no open drain control register.
9.2.5 Pull-up Control Register (PxBPC)
When the external VDD drops below the V
BODR
level, the ports can be selectively configured as input
ports with pull-up resistors activated regardless of the PxnIO. In this case, the port direction is
changed by hardware automatically. If PxnBPC is written logic one, this function is enabled. If
PxnBPC is written logic zero, the port maintain its status even if the external VDD is fallen below the
V
BODR
level.
