MC96FR116C
70
November, 2018 Rev.1.8
11. Peripheral Units
11.1 Clock Generator
11.1.1 Overview
The clock generator module plays a main role in making a stable operating clock, SCLK. There are
two clock sources in MC96FR116C, which are the output of main oscillator connected to the XIN and
XOUT pins and the output of INT-RC oscillator. The clock input is divided by 1.5, 2 or 3, and one of
the divided clocks is used as internal operating clock, SCLK, according to the DIV[1:0] bits in SCCR
register. By default, frequency of SCLK is divided by 3 for INT-RC oscillator.
11.1.2 Block Diagram
Main
OSC
XIN
XOUT
RING
OSC
(1MHz)
P
re
sc
a
le
r
÷1
÷3
÷1.5
÷2
SCLK
(System Clock)
÷ 256
P
re
sc
a
le
r
÷16
÷2048
÷32
. . .
3
BCK
BCLKS
BIT
WDT
BIT
Overflow
2
DIV
CLKSEL
1
0
0
1
SCLK
(System Clock)
INT-RC
OSC
(12MHz)
Figure 11-1 Block Diagram of Clock Generator
