MC96FR116C
136
November, 2018 Rev.1.8
0
Interrupt from Wake is inhibited
1
When WAKE is set, request an interrupt
TXE
Enables the transmitter unit.
0
Transmitter is disabled
1
Transmitter is enabled
RXE
Enables the receiver unit.
0
Receiver is disabled
1
Receiver is enabled
UARTEN
Activate UART module by supplying clock.
0
UART is disabled (clock is halted)
1
UART is enabled
U2X
This bit only has effect for the asynchronous operation and selects
receiver sampling rate.
0
Normal asynchronous operation
1
Double Speed asynchronous operation
UCTRL03 (UART0 Control 3 Register)
E4
H
7
6
5
4
3
2
1
0
-
LOOPS
-
-
-
USBS
TX8
RX8
R
R
R
R
R
R/W
R/W
R/W
Initial value : 00
H
LOOPS
Controls the Loop Back mode of UART, for test mode
0
Normal operation
1
Loop Back mode
1
SS output to other slave device
USBS
Selects the length of stop bit.
0
1 Stop Bit
1
2 Stop Bit
TX8
The ninth bit of data frame. Write this bit first before loading the UDATA
register.
0
MSB (9
th
bit) to be transmitted is ‘0’
1
MSB (9
th
bit) to be transmitted is ‘1’
RX8
The ninth bit of data frame. Read this bit first before reading the receive
buffer.
0
MSB (9
th
bit) received is ‘0’
1
MSB (9
th
bit) received is ‘1’
USTAT0 (UART0 Status Register)
E5
H
7
6
5
4
3
2
1
0
UDRE
TXC
RXC
WAKE
SOFTRST
DOR
FE
PE
R/W
R/W
R/W
R/W
R/W
R
R
R
Initial value : 80
H
UDRE
The UDRE flag indicates if the transmit buffer (UDATA) is ready to be
loaded with new data. If UDRE is ‘1’, it means the transmit buffer is
empty and can hold one or two new data. This flag can generate an
UDRE interrupt. Writing ‘0’ to this bit position will clear UDRE flag.
0
Transmit buffer is not empty.
1
Transmit buffer is empty.
