MC96FR116C
November, 2018 Rev.1.8
111
captured to this register at the second falling edge (when PHASE
bit is ‘0’) or second rising edge (when PHASE bit is ‘1’) of input
carrier signal. This register is initialized by setting WTCL bit in
WTMR.
The WT interrupt is requested only when overflow condition occurs. That is when WT is in IR capture
mode, the interrupt is not issued even when capture event is generated.
