MC96FR116C
November, 2018 Rev.1.8
135
UCTRL03
E4
H
R/W
00
H
UART0 Control 3 Register
USTAT0
E5
H
R
80
H
UART0 Status Register
UBAUD0
E6
H
R/W
FF
H
UART0 Baud Rate Generation Register
UDATA0
E7
H
R/W
FF
H
UART0 Data Register
Table 11-17 Register map of UART
11.9.9 Register Description
UCTRL01 (UART0 Control 1 Register)
E2
H
7
6
5
4
3
2
1
0
-
-
UPM1
UPM0
USIZE2
USIZE1
USIZE0
-
R
R
R/W
R/W
R/W
R/W
R/W
R
Initial value : 00
H
UPM[1:0]
Selects Parity Generation and Check methods
UPM1
UPM0
Parity mode
0
0
No Parity
0
1
Reserved
1
0
Even Parity
1
1
Odd Parity
USIZE[2:0]
When in asynchronous or synchronous mode of operation, selects the
length of data bits in frame.
USIZE2
USIZE1 USIZE0
Data length
0
0
0
5 bit
0
0
1
6 bit
0
1
0
7 bit
0
1
1
8 bit
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
9 bit
UCTRL02 (UART0 Control 2 Register)
E3
H
7
6
5
4
3
2
1
0
UDRIE
TXCIE
RXCIE
WAKEIE
TXE
RXE
UARTEN
U2X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00
H
UDRIE
Interrupt enable bit for UART Data Register Empty.
0
Interrupt from UDRE is inhibited (use polling)
1
When UDRE is set, request an interrupt
TXCIE
Interrupt enable bit for Transmit Complete.
0
Interrupt from TXC is inhibited (use polling)
1
When TXC is set, request an interrupt
RXCIE
Interrupt enable bit for Receive Complete
0
Interrupt from RXC is inhibited (use polling)
1
When RXC is set, request an interrupt
WAKEIE
Interrupt enable bit for Asynchronous Wake in STOP mode. When
device is in stop mode, if RXD goes to LOW level an interrupt can be
requested to wake-up system.
