MC96FR116C
90
November, 2018 Rev.1.8
0
Stops counting
1
Clear counter and starts up-counting
T1DR (Timer 1 Data Register, Write Case)
B5
H
7
6
5
4
3
2
1
0
T1D7
T1D6
T1D5
T1D4
T1D3
T1D2
T1D1
T1D0
W
W
W
W
W
W
W
W
Initial value : FF
H
T1D[7:0]
T1 Compare data
PWM1PR (Timer 1 PWM Period Register, Write Case)
B5
H
7
6
5
4
3
2
1
0
T1PP7
T1PP6
T1PP5
T1PP4
T1PP3
T1PP2
T1PP1
T1PP0
W
W
W
W
W
W
W
W
Initial value : FF
H
T1PP[7:0]
Period of PWM waveform
T1 (Timer 1 Register, Read Case)
B6
H
7
6
5
4
3
2
1
0
T17
T16
T15
T14
T13
T12
T11
T10
R
R
R
R
R
R
R
R
Initial value : 00
H
T1[7:0]
T1 Counter value
PWM1DR (Timer 1 PWM Duty Register, Write Case)
B6
H
7
6
5
4
3
2
1
0
T1PD7
T1PD6
T1PD5
T1PD4
T1PD3
T1PD2
T1PD1
T1PD0
W
W
W
W
W
W
W
W
Initial value : 00
H
T1PD[7:0]
Duty of PWM waveform. NOTE) This register is meaningful only
when PWM1E bit in T1CR register is ‘1’.
CDR1 (Capture 1 Data Register, Read Case)
B6
H
7
6
5
4
3
2
1
0
CDR17
CDR16
CDR15
CDR14
CDR13
CDR12
CDR11
CDR10
R
R
R
R
R
R
R
R
Initial value : 00
H
CDR1[7:0]
T1 Capture value
PWM1HR (Timer 1 PWM High Register)
B7
H
7
6
5
4
3
2
1
0
T1_PE
-
-
-
PW1H3
PW1H2
PW1H1
PW1H0
