MC96FR116C
154
November, 2018 Rev.1.8
11.10.10 I
2
C Register description
I
2
C Registers are composed of I
2
C Mode Control Register (I2CMR), I
2
C Status Register (I2CSR),
SCL Low Period Register (I2CSCLLR), SCL High Period Register (I2CSCLHR), SDA Hold Time
Register (I2CSDAHR), I
2
C Data Register (I2CDR), and I
2
C Slave Address Register (I2CSAR).
11.10.11 Register description for I
2
C
I2CMR (I
2
C Mode Control Register)
9C
H
7
6
5
4
3
2
1
0
IIF
IICEN
RESET
INTEN
ACKEN
MASTER
STOP
START
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
Initial value : 00
H
IIF
This is interrupt flag bit.
0
No interrupt is generated or interrupt is cleared
1
An interrupt is generated
IICEN
Enable I
2
C Function Block (by providing clock)
0
I
2
C is inactive
1
I
2
C is active
RESET
Initialize internal registers of I
2
C.
0
No operation
1
Initialize I
2
C, auto cleared
INTEN
Enable interrupt generation of I
2
C.
0
Disable interrupt, operates in polling mode
1
Enable interrupt
ACKEN
Controls ACK signal generation at ninth SCL period.
Note) ACK signal is output (SDA=0) for the following 3 cases.
When received address packet equals to SLA bits in I2CSAR
When received address packet equals to value 0x00 with GCALL
enabled
When I
2
C operates as a receiver (master or slave)
0
No ACK signal is generated (SDA=1)
1
ACK signal is generated (SDA=0)
MASTER
Represent operating mode of I
2
C
0
I
2
C is in slave mode
1
I
2
C is in master mode
STOP
When I
2
C is master, generates STOP condition.
0
No operation
1
STOP condition is to be generated
START
When I
2
C is master, generates START condition.
0
No operation
1
START or repeated START condition is to be generated
