MC96FR116C
166
November, 2018 Rev.1.8
NOTE
Unlike other reset sources, BOD reset does not take place as soon as BODR goes HIGH(=voltage drops
below BOD stop level). On detecting low voltage while the device is in normal run mode, the device enters
BOD(STOP) mode first. And then by detecting voltage rise, the power control logic wakes the device up to give a
reset signal.
Caution
: When the device is in STOP mode by CPU command(PCON=0x03), the BOD cannot
detect voltage drop because the BOD is disabled to reduce power consume. In this case, the BOD
reset may be issued when a wake-up event or interrupt is generated with the external voltage below
the BOD stop level.
13.4 Noise Canceller for External Reset Pin
A glitch-like or short pulse on external reset pin(P15) is ignored by the dedicated noise-canceller. To
have an effect as a reset source, P15 port should be maintained low continuously at least 8us of
time(T
RNC
) in typical condition. The T
RNC
may vary from 4.8us up to 13.8us according to the condition
of manufacturing process.
13.5 Power-On-RESET
When power is initially applied to the MCU, or when the supply voltage drops below the V
POR
level,
the POR circuit will cause a reset condition. Owing to presence of POR, the external reset pin can be
used as a normal I/O pin. Thus additional resistor and capacitor can be removed to be connected to
reset pin.
t > T
RNC
t > T
RNC
t > T
RNC
t < T
RNC
t < T
RNC
A
A’
A : Reset Input to Noise Canceller
A
’ : Reset output of Noise Canceller
VDD
nPOR
(Internal Signal)
Internal RESETb
Oscillation
BIT Starts
BIT Overflows
Fast VDD Rise Time
V
POR
Figure 13-2 Noise Cancelling of External Reset Pin
Figure 13-3 Reset Release Timing when Power is supplied (VDD Rises Rapidly)
