MC96FR116C
132
November, 2018 Rev.1.8
11.9.6.4 Disabling Transmitter
Disabling the Transmitter by clearing the TXE bit will not become effective until ongoing transmission
is completed. When the Transmitter is disabled, the TXD pin is used as normal General Purpose I/O
(GPIO) or primary function pin.
11.9.7 UART Receiver
The UART Receiver is enabled by setting the RXE bit in the UCTRL1 register. When the Receiver is
enabled, the normal pin operation of the RXD pin is overridden by the UART as the serial input pin of
the Receiver. The baud-rate, mode of operation and frame format must be set before starting serial
reception.
11.9.7.1 Receiving RX data
The Receiver starts data reception when it detects a valid start bit (LOW) on RXD pin. Each bit after
start bit is sampled at pre-defined baud-rate and shifted into the receive shift register until the first stop
bit of a frame is received. Even if there
’
s 2
nd
stop bit in the frame, the 2
nd
stop bit is ignored by the
Receiver. That is, receiving the first stop bit means that a complete serial frame is present in the
receiver shift register and the contents of shift register are to be moved into the receive buffer. The
receive buffer is read by reading the UDATA register.
If 9-bit characters are used (USIZE[2:0] = 7) the ninth bit is stored in the RX8 bit position in the
UCTRL3 register. The 9
th
bit must be read from the RX8 bit before reading the low 8 bits from the
UDATA register. Likewise, the error flags FE, DOR, PE must be read before reading the data from
UDATA register. This is because the error flags are stored in the same FIFO position of the receive
buffer.
11.9.7.2 Receiver flag and interrupt
The UART Receiver has one flag that indicates the Receiver state.
The Receive Complete (RXC) flag indicates whether there are unread data present in the receive
buffer. This flag is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty. If the Receiver is disabled (RXE=0), the receiver buffer is flushed and the RXC flag is
cleared.
When the Receive Complete Interrupt Enable (RXCIE) bit in the UCTRL2 register is set and Global
Interrupt is enabled, the UART Receiver Complete Interrupt is generated while RXC flag is set.
The UART Receiver has three error flags which are Frame Error (FE), Data Overrun (DOR) and Parity
Error (PE). These error flags can be read from the USTAT register. As data received are stored in the
2-level receive buffer, these error flags are also stored in the same position of receive buffer. So,
before reading received data from UDATA register, read the USTAT register first which contains error
flags.
The Frame Error (FE) flag indicates the state of the first stop bit. The FE flag is zero when the stop bit
was correctly detected as one, and the FE flag is one when the stop bit was incorrect, i.e. detected as
zero. This flag can be used for detecting out-of-sync conditions between data frames.
