MC96FR116C
November, 2018 Rev.1.8
81
11.4.2.3 16-bit Timer/Counter Mode
When Timer 0, 1 are configured as 16-bit Timer/Counter Mode, Timer 0 becomes the lower part of the
new 16-bit counter. When the lower 8-bit counter T0 matches T0DR and higher 8-bit counter T1
matches T1DR simultaneously, a 16-bit timer interrupt is issued via Timer 0 interrupt(not Timer 1).
Both T0 and T1 should use the same clock source, which leads to the configuration, T1CK1=1,
T1CK0=1 and 16BIT=1 in T1CR register. This means to use two separate 8-bit counters(T0, T1) as a
single 16-bit counter, T1 must be clocked by the clock source of T0. This is shown in the following
figure.
In 8-bit Timer/Counter Mode, timer output is toggled and appears on P00(P01) port whenever T0(T1)
matches T0DR(T1DR). In 16-bit Timer/Counter Mode, timer output is toggled and appears on P01
port whenever T1+T0 matches T1DR+T0DR. The initial value of each timer
’s output is ‘0’ and output
frequency is calculated by the following equation.
)
1
(
Value
Prescaler
2
Frequency
Clock
Timer
TnDR
COMP
f
where f
COMP
is the frequency of timer output, TnDR is T0DR or T1DR in 8-bit timer mode or
concatenated T1DR+T0DR in 16-bittimer mode.
To observe timer output via port, T0_PE in T0CR register or T1_PE in PWM1HR register must be set.
÷4096
÷1024
÷256
P
r
e
s
c
a
l
e
r
÷2
÷4
÷16
÷64
EC0
SCLK
[B5
H
]
T0IF
Timer0
Interrup
t
16-bit Counter
16-bit Data Register
F/F
P00/T0
PIN
T0EN&T0CN
Clear
[B6
H
]
Comparator
T0ST
T0CK[2:0]
3
T1
(8-bit)
T0
(8-bit)
T1DR
(8-bit)
T0DR
(8-bit)
[B3
H
]
[B3
H
]
POL1
16BIT
CAP1
T1CK1 T1CK0
T1CN
T1ST
T0EN
T0_PE
CAP0
T0CK2 T0CK1 T0CK0
T0CN
T0ST
T1CR
T0CR
1
X
0
X
X
X
X
X
X
1
0
0
1
1
X
X
ADDRESS : B2
H
INITIAL VALUE : 0000_0000
B
ADDRESS : B4
H
INITIAL VALUE : 0000_0000
B
Figure 11-8 Block Diagram of Timer 0, 1 in 16-bit Timer/ Counter mode
