MC96FR116C
November, 2018 Rev.1.8
159
12.4 STOP mode
The least power consuming state called STOP mode is initiated by writing 03
H
to Power Control
Register (PCON, 87
H
). In STOP mode, all analog and digital blocks including main oscillator stop
operation. The analog block VDC also enters its own stop mode and BOD is auto-disabled, so power
consumption is radically reduced. All registers value or RAM data are reserved.
STOP mode release is done by a reset or external pin interrupt request. When a reset is detected in
STOP mode, the device is initialized, so all registers except for BODR register is reset to initial state.
BODR register may or may not be initialized
‘cause it has reset flags which are affected only by its
specific reset source. There
’re three kinds of reset sources which can be used to release STOP mode,
power on reset(nPOR), external reset(P15) and BOD reset.
When a reset or interrupt occurs in STOP mode, the clock control logic makes system clock active
when a pre-defined time is passed. The oscillation stability time can be calculated by the overflow
period of BIT counter.
NOTE
External
Interrupt
XIN
Normal Operation
Release
CPU Clock
SLEEP Mode
Normal Operation
XIN
CPU Clock
RESETB
Normal Operation
BIT Counter
SLEEP Mode
Normal Operation
Release
Set PCON
to 01
Clear & Start
TST = 32ms @ 4Mhz
𝐓𝐒𝐓
𝟏
𝐟𝐗𝐈𝐍
× 𝟐𝟎𝟒𝟖 × 𝟐𝟓𝟔
m-2
m-1
m
n
0
0
0
1
FD
FE
FF
0
1
T
XIN
= 1/f
XIN
f
XIN
= 4MHz
PRD[2:0] in BCCR = 111
B
BCK[2:0] in BCCR = 101
B
64 T
XIN
Figure 12-1 Wake-up from SLEEP mode by an interrupt
Figure 12-2 SLEEP mode release by an external reset
