MC96FR116C
November, 2018 Rev.1.8
57
10.3 Block Diagram
EA
(IE.7[A8
H
])
IE3[AB
H
]
BIT
FLASH
INT18
INT19
IE2[AA
H
]
INT15
INT16
INT17
INT12
INT13
INT14
Timer 1
WDT
WT
REMOCON
Timer 3
Timer 2
EIEDGE
EIPOLA
IE[A8
H
]
FLAG3
FLAG4
FLAG5
FLAG0
FLAG1
FLAG2
INT0
INT1
INT2
INT3
INT4
INT5
EIFLAG.0[`AC
H
]
IE1[A9
H
]
INT9
INT10
INT11
INT6
INT7
INT8
IRI
Timer 0
UART TX0
UART RX0
BODIF
EIFLAG.1[`AC
H
]
EIFLAG.2[`AC
H
]
EIFLAG.3[`AC
H
]
EIFLAG.4[`AC
H
]
EIFLAG.5[`AC
H
]
USTAT0.5 [E5
H
]
USTAT0.7/6 [E5
H
]
RMR.7[E8
H
]
WTMR.4[D4
H
]
WDTMR.0[8D
H
]
KEYSCAN
PCI0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
IP[B8
H
]
IP1[F8
H
]
Release
Stop/Sleep
Priority High
Priority Low
Figure 10-2 Block Diagram of Interrupt Controller
