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MC96FR116C

38

November, 2018 Rev.1.8

7.16 REM_OD_OUT PORT CHARACTERISTICS

The characteristics of REM_OD_OUT is related with VDD_IR, not VDD.

7.17 TYPICAL CHARACTERISTICS

These graphs and tables provided in this section are for design guidance only and are not tested or

guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g.

outside specified VDD range). This is for information only and devices are guaranteed to operate

properly only within the specified range.

The data presented in this section is a statistical summary of data collected on units from different lots
over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents
(mean + 3σ) and (mean - 3σ) respectively where σ is standard deviation.

Figure 7-5 Characteristics for REM_OD_OUT

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Summary of Contents for MC96FR116C Series

Page 1: ...MC96FR116C November 2018 Rev 1 8 1 ABOV SEMICONDUCTOR Co Ltd 8 BIT MICROCONTROLLERS MC96FR116C User s Manual Rev 1 8...

Page 2: ...s of REM_PP_OUT REM_OD_OUT are added The max current of stop mode is changed from 15uA to 10uA 9 2 7 Register Map The initial value of P0BPC is changed from 0x00 to 0xFF The initial value of P1BPC is...

Page 3: ...hanged FLTEN IRCC0 3 is added IRCC3 is added 7 11 DC CHARACTERISTICS IOL VDD 3 3V is changed from 18mA to 16mA 7 12 AC CHARACTERISTICS Minimum tIW is added Minimum tRST is added tREM_OD_R and tREM_OD_...

Page 4: ...5 15 45 QFN 12MHz 2 0 20 70 12MHz 1 0 15 45 1 3 Ordering Information 3 PIN CONFIGURATION 4 PACKAGE DIMENSION The information of 16 QFN is added 7 8 Internal RC Oscillator CHARACTERISTICS The informat...

Page 5: ...PERATING CONDITION 30 7 3 POWER SEQUENCE CHARACTERISTICS 30 7 4 VOLTAGE DROPOUT CONVERTER 1 8V Internal regulator CHARACTERISTICS 31 7 5 BROWN OUT DETECTOR BOD CHARACTERISTICS 31 7 6 RAM Data Retentio...

Page 6: ...g Timer WDT 75 11 4 TIMER PWM 77 11 5 Watch Timer with event capture function WT 106 11 6 IR Capture Control IRCC 112 11 7 Carrier Generator 116 11 8 Key Scan 124 11 9 UART 127 11 10 I2 C 141 12 POWER...

Page 7: ...8 7 15 1 Overview 179 15 2 Boot Area 179 15 3 Register Map 180 15 4 Register Description 181 15 5 Memory map 187 15 6 Serial In System Program Mode 188 15 7 Security 192 16 FUSE 193 16 1 FUSE Control...

Page 8: ...ure 8 2 DATA MEMORY IRAM 40 Figure 8 3 Lower 128 Byte of IRAM 41 Figure 8 4 PSW Register 43 Figure 8 5 DATA MEMORY XRAM 44 Figure 10 1 External Interrupt trigger condition 56 Figure 10 2 Block Diagram...

Page 9: ...tch Timer in IR capture mode 107 Figure 11 26 Timing Diagram of Watch Timer in IR capture mode 107 Figure 11 27 Block Diagram of IR Capture function 112 Figure 11 28 Block Diagram of IR Learning 112 F...

Page 10: ...when Power is supplied VDD Rises Slowly 167 Figure 13 5 Fuse Configuration Value Read Timing after Power On 167 Figure 13 6 Operation according to Power Level 168 Figure 13 7 Reset procedure due to e...

Page 11: ...rge current drivability specialized for remote control application Additionally the MC96FR116C supports power saving modes to reduce power consumption NOTE1 In this document the ROM means non volatile...

Page 12: ...tor WLCSP 12MHz 1 0 20 70 User Trim 12MHz 0 5 15 45 User Trim 16QFN 20TSSOP 12MHz 2 0 20 70 User Trim 12MHz 1 0 15 45 User Trim Operating Frequency 1 12MHz X Tal oscillator 12 8 6 4MHz Internal RC osc...

Page 13: ...mber 2018 Rev 1 8 13 1 3 1 Device Nomenclature Device nomenclature MC96FR116Cx Family Name Package type RoHS Packing MC96FR116Cx R N T U QFN R TSSOP Halogen Free T Tape Reel B W WLCSP Figure 1 1 Devic...

Page 14: ...a user code to read and modify the internal memory or SFR Special Function Register s And also OCD controls MCU s internal debugging logic which means OCD controls emulation step run monitoring etc OC...

Page 15: ...wait for a period of time from internal pull up high to low the internal controller for entering test mode is initialized Then when DSCA and DSCA appointed communication the test mode is entered As d...

Page 16: ...rammer To program or download user code into the ROM of MC96FR116C ABOV semiconductor provides several tools As a single programmer which can program only one chip at a time there are E PGM and PGMPlu...

Page 17: ...es PGMPlusLC II is low cost writing tool USB interface is supported No need for USB driver installation Connect to the external power adaptor 5V 2A Fast 32 bit Cortex M3 MCU is used Support high volta...

Page 18: ...rammer E GANG4 6 can program maximum4 6 MCUs at a time So it is mainly used in mass production line As gang programmer is standalone type it does not require host PC 2 VDD 4 GND 6 Serial Clock DSCL 8...

Page 19: ...SH 16KB Power On Reset Brown Out Detector CARRIER GENERATOR P03 T1 PWM1 P02 EC0 P03 T0 P01 T2 P05 PWM3 P00 INT0 P01 INT1 P02 INT2 P03 INT3 P04 INT4 P05 INT5 P05 P00 P15 P10 Voltage Down Converter P13...

Page 20: ...A4 B2 B1 B3 B4 C2 C1 C3 C4 1 2 3 4 A P11 DSDA VDD VDD_IR VSS B P10 DSCL REMOUT_PP P12 REMOUT_OD P13 XIN C P05 INT5 TXD P03 INT3 SDA P14 XOUT P15 RESETB D P04 INT4 RXD P02 INT2 SCL P01 INT1 P00 INT0 16...

Page 21: ...0 9 5 6 7 8 16 15 14 13 MC96FR116CU 16QFN EP OPEN VSS P13 XIN P14 XOUT P15 RESETB P11 DSDA P10 DSCL P05 INT5 TXD PWM3 P04 INT4 RXD REM_OD SENSOR VDD_IR VDD P12 REM_PP P00 INT0 SS P11 INT1 SCK T2 P02 I...

Page 22: ...1 2 3 4 5 6 7 8 16 15 14 13 12 11 VDD_IR REM_OD SENSOR VSS P13 XIN P14 XOUT P15 RESETB P16 P17 P07 P06 P05 INT5 TXD PWM3 P04 INT4 RXD P03 INT3 T0 PWM1 P02 INT2 9 18 17 10 19 P12 REM_PP 20 VDD P00 INT0...

Page 23: ...MC96FR116C November 2018 Rev 1 8 23 4 PACKAGE DIMENSION Figure 4 1 PKG DIMENSION 16 WLCSP...

Page 24: ...MC96FR116C 24 November 2018 Rev 1 8 Figure 4 2 PKG DIMENSION 16 QFN...

Page 25: ...MC96FR116C November 2018 Rev 1 8 25 Figure 4 3 PKG DIMENSION 20 TSSOP...

Page 26: ...NOTE1 SDA T0 PWM1 P04 INT4 NOTE1 RXD0 EC3 P05 INT5 NOTE1 TXD0 P10 I O 3 bit I O port P1 Can be set in input or output mode bitwise Internal pull up resistor can be activated by setting PxnPU bit in Px...

Page 27: ...8V to ExtVDD LevelShift ExtVDD to 1 8V Px data PxOD open drain PxPU pull up selection SUB FUNC DATA OUTPUT PxIO direction SUB FUNC DIRECTION 0 1 MUX MUX 1 0 PORTx INPUT SUB FUNC ANALOG CHANNEL ENABLE...

Page 28: ...A OUTPUT PxIO direction SUB FUNC DIRECTION 0 1 MUX MUX 1 0 PORTx INPUT SUB FUNC DATA INPUT ANALOG CHANNEL ANALOG INPUT 0 1 MUX r D CP Q VDD EXTERNAL INTERRUPT INTERRUPT ENABLE EDGE REG FLAG CLEAR POLA...

Page 29: ...MC96FR116C November 2018 Rev 1 8 29 6 3 REM_PP_OUT Port 6 4 REM_OD_OUT Port Figure 6 4 REM_OD_OUT port Figure 6 3 REM_PP_OUT port...

Page 30: ...s beyond those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability 7 2 RECOMMEN...

Page 31: ...voltage level the BOD detects the power condition and makes the device enter STOP like mode called BOD mode When the external power is restored a BOD reset is generated according to pre defined seque...

Page 32: ...15 40 11 880 12 12 120 MHz 20 70 11 760 12 12 240 VDD VBODR 3 6V 15 40 11 844 12 12 156 20 70 11 724 12 12 276 Table 7 9 Internal RC Oscillator Characteristics QFN 7 9 Internal RING Oscillator CHARAC...

Page 33: ...P0 and P1 VOL VDD 3 3V IOL 16mA 0 4 0 5 V VDD 1 8V IOL 7mA 0 4 0 5 Output High Voltage of P0 and P1 VOH VDD 3 3V IOH 6mA VDD 0 5 V VDD 1 8V IOH 2mA VDD 0 5 Output Low Voltage of REM_PP_OUT VOL_REM_PP...

Page 34: ...ns External Clock Transition Time tRCP tFCP XIN 10 ns Interrupt Input Width tIW INT0 INT5 5 10 ns RESETB Input Pulse L Width tRST RESETB 4 8 us Rising time of REM_OD_OUT TRODSR PMISC 4 0 VDD_IR 3 3V...

Page 35: ...MC96FR116C November 2018 Rev 1 8 35 XIN 0 9VDD 0 1VDD 1 fMCP tCPW tCPW tRCP tFCP EC0 0 8VDD 0 2VDD tIW tIW tRST 0 2VDD 0 8VDD 0 2VDD tECW tECW INT0 INT5 RESETB tREC tFEC Figure 7 1 AC Timing...

Page 36: ...period of the SCL clock tLOW 4 7 1 3 Us HIGH period of the SCL clock tHIGH 4 0 0 6 us Setup time for a repeated START condition tSU STA 4 7 0 6 us Data hold time tHD DAT 0 3 45 0 0 9 us Data setup tim...

Page 37: ...cs of REM_PP_OUT is related with VDD not VDD_IR 6 5 4 3 2 1 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 VOL V IOL mA VDD 2V VDD 3V VDD 4V 0 5 10 15 20 25 30 VOH V 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 VDD 2V VDD...

Page 38: ...the data presented are outside specified operating range e g outside specified VDD range This is for information only and devices are guaranteed to operate properly only within the specified range The...

Page 39: ...vice 8 1 Program Memory A 16 bit program counter is capable of addressing up to 16K bytes but this device has 16K bytes of program memory space located in one bank 0 The following figure shows a map o...

Page 40: ...are grouped into 4 banks of 8 registers Program instructions call out these registers as R0 through R7 Two bits in the Program Status Word PSW select which register bank is in use This allows more eff...

Page 41: ...2 2 Direct And Indirect Address Area The 128 bytes of RAM which can be accessed by both direct and indirect addressing can be divided into 3 segments as listed below and shown in Figure 8 3 00 01 02 0...

Page 42: ...thin the core not as RAM The MC96FR116C has special registers which are provided by M8051 core These are Program Counter PC Accumulator A B register B the Stack Pointer SP the Program Status Word PSW...

Page 43: ...RS0 and RS1 are used to select one of the four register banks shown in Figure 8 3 A number of instructions refer to these RAM locations as R0 through R7 The selection of which of the four banks is be...

Page 44: ...through 07FFH This address space is assigned to XDATA NOTE region and used for data storage NOTE XRAM 32Bytes of page buffers and some extended SFR XSFR are assigned to XDATA area in MC96FR116C And th...

Page 45: ...T3L CDR3L PWM3DRL T3H CDR3H PWM3DRH T3DRL PW M3PRL T3DRH PW M3PRH T2L T2DRL CDR2L C0H P0PC 0000_0000 RDBH RDBL RDRH RDRL T2CR T2H T2DRH CDR2H B8H IP 00_0000 RDCH CFRH CFRL RDCL RODR ROB B0H EIENAB T0C...

Page 46: ...PBUF_08 PBUF_09 PBUF_0A PBUF_0B PBUF_0C PBUF_0D PBUF_0E PBUF_0F 8000H PBUF_00 PBUF_01 PBUF_02 PBUF_03 PBUF_04 PBUF_05 PBUF_06 PBUF_07 2F68H FSUBA0 FSUTA1 FSUTA0 FSCTRL 2F60H FSLBA1 FSLBA0 FSLTA1 FSLTA...

Page 47: ...W R W Initial value 00H B B Register SP Stack Pointer 81H 7 6 5 4 3 2 1 0 SP R W R W R W R W R W R W R W R W Initial value 07H SP Stack Pointer DPL Data Pointer Low Byte 82H 7 6 5 4 3 2 1 0 DPL R W R...

Page 48: ...ontains an odd number of 1s otherwise it is reset to 0 EO Extended Operation Register A2H 7 6 5 4 3 2 1 0 TRAP_EN DPSEL 2 DPSEL 1 DPSEL 0 R R R R W R R W R W R W Initial value 00H TRAP_EN Select the i...

Page 49: ...e of pull up resistor If PxnPU is written logic one the pull up resistor is activated If PxnPU is written logic zero the pull up resistor is deactivated When the port is configured as an input port in...

Page 50: ...n Register P0PU 2F00H R W 00H P0 Pull up Resistor Selection Register P1OD 2F08H R W 00H P0 Open drain Selection Register P0BPC 2F50H R W FFH P0 Pull up Control Register P0PC C1H R W 00H P0 Pin Change...

Page 51: ...W R W R W R W R W Initial value 00H P0PU 7 0 P0 Pull up Control 0 Disable pull up 1 Enable pull up P0OD P0 Open drain Selection Register 2F08H 7 6 5 4 3 2 1 0 P07OD P06OD P05OD P04OD P03OD P02OD P01OD...

Page 52: ...R W R W R W R W R W R W R W R W Initial value 00H P1 7 0 I O Data P1IO P1 Direction Register A0H 7 6 5 4 3 2 1 0 P17IO P16IO P15IO P14IO P13IO P12IO P11IO P10IO R W R W R W R W R W R W R W R W Initial...

Page 53: ...rt Miscellaneous 0 Register 2F11H 7 6 5 4 3 2 1 0 TRODEN TRPPEN R R R R R R R W R W Initial value 00H TRPPEN REMOUT push pull transistor control 0 REMOUT push pull transistor is disabled 1 REMOUT push...

Page 54: ...mparator output Dynamic pull up is used with IRPUST1 and IRPUST2 0 Disable 1 Enable TRODSR The fast slew rate of REM_OD_OUT control Refer to tREM_OD_R and tREM_OD_F of 7 12 AC CHARACTERISTICS 0 Disabl...

Page 55: ...ned to 6 groups and each group can have different priority according to IP and IP1 registers By default all interrupt sources are level triggered but external interrupts can be set to operate in edge...

Page 56: ...the interrupt will trigger as long as the pin is held low or high External interrupts are detected asynchronously This implies that these interrupts can be used for wake up sources from stop mode The...

Page 57: ...INT8 IRI Timer 0 UART TX0 UART RX0 BODIF EIFLAG 1 ACH EIFLAG 2 ACH EIFLAG 3 ACH EIFLAG 4 ACH EIFLAG 5 ACH USTAT0 5 E5H USTAT0 7 6 E5H RMR 7 E8H WTMR 4 D4H WDTMR 0 8DH KEYSCAN PCI0 0 1 2 3 4 5 6 7 8 9...

Page 58: ...REMOCON INT15 IE2 3 16 Maskable 007BH WT INT16 IE2 4 17 Maskable 0083H WDT INT17 IE2 5 18 Maskable 008BH BIT INT18 IE3 0 19 Maskable 0093H FLASH INT19 IE3 1 20 Maskable 009BH KEYSCAN INT20 IE3 2 21 M...

Page 59: ...l enable bit INTnE in IEx register must be enabled At this time the effective time of interrupt request after setting control registers is as follows Saves PC to stack to continue program execution af...

Page 60: ...evel and the interrupt handler should allow another interrupt request The following example shows how to allow INT0 interrupt request while executing INT1 interrupt service routine In this example INT...

Page 61: ...utine may only be interrupted by an interrupt of higher priority than being serviced And when more than two interrupts are requested at the same time the one of highest priority is serviced first 10 8...

Page 62: ...H DPH PUSH B PUSH ACC Interrupt_Processing POP ACC POP B POP DPH POP DPL POP PSW RETI Figure 10 7 Generating branch address to BIT interrupt service routine from vector table Figure 10 8 Processing Ge...

Page 63: ...ble Register IE1 A9H R W 00H Interrupt Enable Register 1 IE2 AAH R W 00H Interrupt Enable Register 2 IE3 ABH R W 00H Interrupt Enable Register 3 IP B8H R W 00H Interrupt Priority Register IP1 F8H R W...

Page 64: ...same When the group priority is decided by configuring IP and IP1 registers among 4 interrupt sources within the group the lower numbered interrupt has the higher priority 10 12 4 External Interrupt F...

Page 65: ...interrupt request INT5E Enable or disable External Interrupt 5 0 Disable 1 Enable INT4E Enable or disable External Interrupt 4 0 Disable 1 Enable INT3E Enable or disable External Interrupt 3 0 Disable...

Page 66: ...R W R W R W R W R W Initial value 00H INT17E Enable or disable WDT Interrupt 0 Disable 1 Enable INT16E Enable or disable Watch Timer Interrupt 0 Disable 1 Enable INT15E REMOCON Carrier generator Inte...

Page 67: ...egister 1 F8H 7 6 5 4 3 2 1 0 IP15 IP14 IP13 IP12 IP11 IP10 R R R W R W R W R W R W R W Initial value 00H IP 5 0 IP1 5 0 Select Interrupt Group Priority IP1x IPx Description 0 0 Group x is of level 0...

Page 68: ...ode of each external interrupt pin Trigger mode is also affected by the EDGEnF bit 0 External interrupt is triggered by level default 1 External interrupt is triggered by a rising edge EDGEnF Selects...

Page 69: ...PS3 External Interrupt Port Selection 3 Register 2F1BH 7 6 5 4 3 2 1 0 EIPS37 EIPS36 EIPS35 EIPS34 EIPS33 EIPS32 EIPS31 EIPS30 R W R W R W R W R W R W R W R W Initial value 03H EIPS3 3 0 Configure ext...

Page 70: ...output of INT RC oscillator The clock input is divided by 1 5 2 or 3 and one of the divided clocks is used as internal operating clock SCLK according to the DIV 1 0 bits in SCCR register By default fr...

Page 71: ...isabled at stop mode 1 Ring Oscillator is enabled at stop mode DIV 1 0 Selects the divide ratio of operating clock sources XIN and INT RC DIV1 DIV0 Description in case of fINT RC 12MHz 0 0 fINT RC 1 1...

Page 72: ...bit counter used to guarantee oscillator stabilization time when MC96FR116C is reset or waken from STOP mode The BIT counter is clocked by a clock divided from system clock SCLK and the divide ratio...

Page 73: ...4 Register Description BCCR BIT Clock Control Register 8BH 7 6 5 4 3 2 1 0 BITF BCK2 BCK1 BCK0 BCLR PRD2 PRD1 PRD0 R W R W R W R W R W R W R W R W Initial value 57H BITF Reflects the state of BIT int...

Page 74: ...0 1 0 When BITR 2 0 111 0 1 1 When BITR 3 0 1111 1 0 0 When BITR 4 0 11111 1 0 1 When BITR 5 0 111111 1 1 0 When BITR 6 0 1111111 1 1 1 When BITR 7 0 11111111 default NOTE This is the case when the fr...

Page 75: ...rom STOP mode NOTE and also as a general system timer One example is to limit the maximum time allowed for certain operations giving an interrupt when the operation has run longer than expected In Sys...

Page 76: ...00H Watch Dog Timer Counter Register WDTMR 8DH R W 00H Watch Dog Timer Mode Register Table 11 3 Register Map of WDT 11 3 4 WDT Interrupt Timing Source Clock BIT Overflow WDTCR 7 0 WDTR 7 0 WDTIF Inter...

Page 77: ...TCR4 WDTCR3 WDTCR2 WDTCR1 WDTCR0 R R R R R R R R Initial value 00H WDTCR 7 0 The value of WDT counter WDTMR Watch Dog Timer Mode Register 8DH 7 6 5 4 3 2 1 0 WDTEN WDTRSON WDTCL WDTIFR R W R W R W R W...

Page 78: ...generated on INT0 or INT1 pins In 8 16 bit Timer Counter Mode Timer 0 compares counter value with the value in timer data register and when counter reaches to the compare value the timer output is tog...

Page 79: ...divide ratio is decided by T0CK 2 0 and T1CK 2 0 bits When the external clock EC0 is selected as a clock source the counter increases at rising edge of the clock When the counter value of each 8 bit...

Page 80: ...0DR T1DR Occur Interrupt Occur Interrupt Occur Interrupt T0DR T1DR Value TIME STOP Timer 0 1 T0IF T1IF Interrupt Occur Interrupt Occur Interrupt Clear Start Disable Enable Up count T0ST T1ST Start Sto...

Page 81: ...Counter Mode timer output is toggled and appears on P01 port whenever T1 T0 matches T1DR T0DR The initial value of each timer s output is 0 and output frequency is calculated by the following equatio...

Page 82: ...T1 is cleared to 00H and counts up again The timer interrupt in Capture Mode is very useful when the interval of capture event on port P36 P37 is longer than the interrupt period of timer That is by c...

Page 83: ...ata Register T0EN T0CN Clear B3H T0ST T0CK 2 0 3 T1CK 1 0 2 INT0 EIEDGE 1 0 B5H INT1IF INT1 Interrupt 8 bit Timer1 Counter T1 8 bit 8 bit Timer1 Data Register CDR1 8 bit T1CN Clear B6H T1ST INT1 EIEDG...

Page 84: ...uest T0F T1F FFH FFH YYH 00H 00H 00H 00H 00H T0 T1 Value Interrupt Request INT0F INT1F TIME 1 2 3 4 5 6 n 2 n 1 n Interrupt Interval Period 0 Count Pulse Period PCP Up count CDR0 CDR1 Load Ext INT0 PI...

Page 85: ...it in T1CR register To output the PWM waveform through T1 PWM1 pin the T1_PE bit in PWM1HR register is to be set The period and duty of PWM waveform are decided by PWM1PR PWM Period Register PWM1DR PW...

Page 86: ...orm high for duty value In other case PWM waveform is low for duty value P r e s c a l e r T0 Clock Source SCLK T1CN T1ST T1CK 1 0 2 1 2 16 8 bit Timer1 PWM Period Register 8 bit Timer1 Counter 2 bit...

Page 87: ...02 T1 PWM1 POL0 1 T1 PWM1 POL0 1 Period Cycle 1 3FFH X250ns 256us 3 9kHz PWM1PR 8 bit PWM1DR 8 bit 1 1 FFH 0 0 80H T1CK 1 0 00H fSCLK PWM1HR 03H PWM1PR FFH PWM1DR 80H Source Clock fSCLK T1 T1 PWM1 PO...

Page 88: ...put Timer 0 output or not through I O pin 0 Timer 0 output does not come out through I O pin 1 Timer 0 output overrides the normal port functionality of I O pin CAP0 Selects operating mode of Timer 0...

Page 89: ...1ST R W R W R W R W R W R W R W R W Initial value 00H POL Selects polarity of PWM 0 PWM waveform is low for duty value 1 PWM waveform is high for duty value 16BIT Selects width of Timer 0 1 0 Timer 0...

Page 90: ...er 1 Register Read Case B6H 7 6 5 4 3 2 1 0 T17 T16 T15 T14 T13 T12 T11 T10 R R R R R R R R Initial value 00H T1 7 0 T1 Counter value PWM1DR Timer 1 PWM Duty Register Write Case B6H 7 6 5 4 3 2 1 0 T1...

Page 91: ...mer 2 can detect the envelope of IR input signal or counts the number of input carrier signal In envelop detection mode of operation the counter value of Timer 2 is captured into timer capture registe...

Page 92: ...H 64 16 P r e s c a l e r 1 2 4 8 SCLK T2CK 2 0 3 256 EC2 or IRSensor EC2E 1 CRF T2EDGE 1 0 T2IF WTIF T2 or WT Interrupt WT Out IRCAP2 IRCAP2 T2EDGE 1 0 00B 0 1 64 16 P r e s c a l e r 1 2 4 8 SCLK C7...

Page 93: ...Mode is enabled by setting T2IR bit in IRCC2 register This mode of operation is only available when IRCEN bit in IRCC1 register is set The clock source is the rising edge of input carrier signal Like...

Page 94: ...imer 2 is a normal counter 1 Timer 2 is an event counter clocked by EC2 T2_PE Controls whether to output Timer 2 output or not through I O pin 0 Timer 2 output does not come out through I O pin 1 Time...

Page 95: ...L3 CDR2L2 CDR2L1 CDR2L0 R R R R R R R R Initial value 00H CDR2L 7 0 T2 Capture Data Low T2H Timer 2 Counter High Read Case C7H 7 6 5 4 3 2 1 0 T2H7 T2H6 T2H5 T2H4 T2H3 T2H2 T2H1 T2H0 R R R R R R R R I...

Page 96: ...of IR input normally amplified carrier signal and overflow of WT When Timer 3 is used to calculate the number of carrier signal the rising edge of input carrier becomes the clock source of Timer 3 For...

Page 97: ...sing edge or both edge When Timer 3 operates in IR capture mode the capture source becomes the output of IR AMP And the T3EDGE 1 0 bits in IRCC2 register select the triggering condition of Watch Timer...

Page 98: ...equested if enabled EC3E PWM3 E T3CK2 T3CK1 T3CK0 T3CN T3ST T3CR X X 1 X X X X X ADDRESS CAH INITIAL VALUE 0000_0000B CCH INT3IF INT3 Interrupt 16 bit Counter 16 bit Capture Register T3CN Clear CBH T3...

Page 99: ...000 250ns T3CK 2 0 001 500ns T3CK 2 0 011 2us 16 bit 60 938Hz 30 469Hz 7 617Hz 15 bit 121 87Hz 60 938Hz 15 234Hz 10 bit 3 9KHz 1 95KHz 0 49KHz 9 bit 7 8KHz 3 9KHz 0 98KHz 8 bit 15 6KHz 7 8KHz 1 95KHz...

Page 100: ...S Q R P03 PWM3 1 2 4 8 16 64 256 CRF P r e s c a l e r SCLK T3REQ T2REQ T0REQ T3_PE POL T1REQ Figure 11 22 Block Diagram of Timer 3 in PWM Mode T3CN T3ST 16 bit Timer3 PWM Period Register 16 bit Timer...

Page 101: ...decided by PWM3PRH and PWM3PRL registers and the duty of PWM3 is decided by PWM3DRH and PWM3DRL registers PWM3PRH and PWM3PRL registers are write only Note that the value of period and duty registers...

Page 102: ...of Timer 3 0 Timer 3 is Normal Timer Counter 1 Timer 1 is PWM CAP3 Selects operating mode of Timer 3 0 Timer Counter mode 1 Capture mode T3CK 2 0 Selects the clock source of Timer 3 NOTE T3CK2 T3CK1...

Page 103: ...E Writing 0 to this bit position clears interrupt flag of each timer T3L Timer 3 Counter Low Read Case CBH 7 6 5 4 3 2 1 0 T3L7 T3L6 T3L5 T3L4 T3L3 T3L2 T3L1 T3L0 R R R R R R R R Initial value 00H T3L...

Page 104: ...DRL6 T3DRL5 T3DRL4 T3DRL3 T3DRL2 T3DRL1 T3DRL0 W W W W W W W W Initial value FFH T3DRL 7 0 T3 Compare Data Low NOTE Be sure to clear PWM3E in T3CR register before loading this register PWM3PRL PWM3 Pe...

Page 105: ...ovember 2018 Rev 1 8 105 7 6 5 4 3 2 1 0 P3PPH7 P3PPH6 P3PPH5 P3PPH4 P3PPH3 P3PPH2 P3PPH1 P3PPH0 W W W W W W W W Initial value FFH P3PPH 7 0 PWM3 Period High NOTE Writing is effective only when PWM3E...

Page 106: ...R1 and WTDR0 registers To read each WTDRH WTDR1 and WTDR0 returns WT_TMR high 6 bit of WTIR and low 8 bit of WTIR counter value When Watch timer operates in IR capture mode the WT is a simple 14 bit u...

Page 107: ...e0 capture2 WT Sync start WT clear WT clear WT clear WT clear WT clear WT clear WT Overflow WT stop Timer2 captures when T2EDGE 1 1 Timer3 captures when T3EDGE 1 1 SENSOR Input P31 WTIR Counter WT Out...

Page 108: ...D1H 7 6 5 4 3 2 1 0 WTEN OVFDIS WTCL WTCK1 WTCK0 R W R W R W R W R W Initial value 00H WTEN Enable Watch Timer 0 Disable WT 1 Enable WT OVFDIS Control auto clear function of WT when counters overflow...

Page 109: ...Interrupt flag of WT This flag bit is cleared when the interrupt is serviced or by writing 0 to this bit field 0 No WT interrupt is generated 1 WT interrupt occurred WTDRH Watch Timer Data Register Hi...

Page 110: ...WTCR1L Watch Timer Capture Register 1 Low F4H 7 6 5 4 3 2 1 0 WTCR107 WTCR106 WTCR105 WTCR104 WTCR103 WTCR102 WTCR101 WTCR100 R R R R R R R R Initial value FFH WTCR1 7 0 When WT is in IR capture mode...

Page 111: ...bit is 0 or second rising edge when PHASE bit is 1 of input carrier signal This register is initialized by setting WTCL bit in WTMR The WT interrupt is requested only when overflow condition occurs Th...

Page 112: ...lso Timer 3 can support IR capture feature Both Timer 2 and Timer 3 can detect the envelop of incoming carrier or count the number of input carrier signal according to the setting of IRCC2 register 11...

Page 113: ...Table 11 11 Register Map of IR Capture Control module 11 6 4 Register Description IRCC0 IR Capture Control Register 0 DDH 7 6 5 4 3 2 1 0 IRAEN FLTEN RSEL2 RSEL1 RSEL0 R W R R R R W R W R W R W Initia...

Page 114: ...led 01 Interrupt is triggered on falling edge of IRI input 10 Interrupt is triggered on rising edge of IRI input 11 Interrupt is triggered on both edge of IRI input IRPOL Select the polarity of WT inp...

Page 115: ...tion of incoming carrier signal These bits should be cleared to 00 when T2 operates in normal capture mode or the WT output becomes capture source of Timer 2 The T2IR bit should be cleared to 0 also 0...

Page 116: ...data pulse generation RDC reaches to RDRH or RDRLNOTE In this case the RDPE bit in RMR should be 1 At each match event an interrupt can be issued The RODR register can also be altered by writing to t...

Page 117: ...Mode Register E8H 7 6 5 4 3 2 1 0 RDIF CEN CCK1 CCK0 RDPE RDCK2 RDCK1 RDCK0 R R W R W R W R W R W R W R W Initial value 00H RDIF Interrupt flag This flag is cleared when the interrupt is serviced RDP...

Page 118: ...R W R W R W R W R W R W Initial value FFH CFH 7 0 Carrier Frequency High Carrier High Interval CFH 7 0 X TCR_CLK TCR_CLK is the period of clock source for CRC counter selected by CCK 1 0 CFRL Carrier...

Page 119: ...nter selected by RDCK 2 0 RDRL Remocon Data Register Low C5H 7 6 5 4 3 2 1 0 RDR15 RDR14 RDR13 RDR12 RDR11 RDR10 RDR9 RDR8 R W R W R W R W R W R W R W R W Initial value FFH RDR 7 0 Remote Data Low Low...

Page 120: ...ter In this way four kinds of signal multiplexing is supported using carrier signal and RODR value The period and frequency of carrier signal and remote data pulse is calculated by the following equat...

Page 121: ...e case carrier signal is off As can be seen only RODR value appears on REMOUT port The difference between previous and below figure is apparent ROB 0 or 1 RDR RDR RDR Match with RDRH RDRL REMOUT ROD R...

Page 122: ...it is 1 the interrupt is requested only when RDPE bit is 1 Even if the interrupt is not required to be serviced by CPU the flag can be read through RMR register And T2DR T3DR T2DR REMOUT CEN 1 RODR tD...

Page 123: ...10 00 11 00 12 00 13 00 14 00 15 00 16 00 17 00 18 00 19 00 20 00 21 00 22 00 23 00 24 00 25 00 26 00 27 00 28 00 29 00 30 00 31 00 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H...

Page 124: ...input sources The key interrupt triggering mode is selected by KITSR register 11 8 2 Block Diagram Internal Key Scan Interrupt 0 1 SRLC07 P07 SMRR07 KS7 0 1 SRLC00 P00 SMRR00 KS0 0 1 SRLC17 P17 SMRR1...

Page 125: ...Initial value 00H SMRR0 7 0 Enables key function of Port 0 pins 0 Key function is not used 1 Key function overrides the normal port functionality of I O pin SMRR1 Standby Mode Release Register 1 D3H...

Page 126: ...W R W R W R W Initial value 00H SRLC1 7 0 Selects the trigger level of key input interrupt when Port 1 is used as key input source 0 Triggered by a low level 1 Triggered by a high level KITSR Key Int...

Page 127: ...plete UART has baud rate generator transmitter and receiver The baud rate generator for asynchronous operation The Transmitter consists of a single write buffer a serial shift register parity generato...

Page 128: ...A 1 Rx TXD Tx Control Stop bit Generator M U X UPM1 Parity Generator Transmit Shift Register TXSR UDATA Tx UPM0 I N T E R N A L B U S L I N E M U X LOOPS TXC TXCIE UDRIE UDRE Empty signal To interrupt...

Page 129: ...d Receiver Table below contains equations for calculating the baud rate in bps Operating Mode Equation for Calculating Baud Rate Normal Mode U2X 0 Double Speed Mode U2X 1 Table 11 16 Equations for Cal...

Page 130: ...s transmitted it can be directly followed by a new frame or the communication line can be set to an idle state The idle means high state of data pin The next figure shows the possible combinations of...

Page 131: ...tate One is UART Data Register Empty UDRE and the other is Transmit Complete TXC Both flags can be interrupt sources UDRE flag indicates whether the transmit buffer is ready to be loaded with new data...

Page 132: ...must be read from the RX8 bit before reading the low 8 bits from the UDATA register Likewise the error flags FE DOR PE must be read before reading the data from UDATA register This is because the erro...

Page 133: ...en the function of UART so RXD pin becomes normal GPIO or primary function pin 11 9 7 5 Asynchronous Data Reception To receive asynchronous data frame the UART includes a clock and data recovery unit...

Page 134: ...peated until a complete frame is received including the first stop bit The decided bit value is stored in the receive shift register in order Note that the Receiver only uses the first stop bit of a f...

Page 135: ...IZE1 USIZE0 Data length 0 0 0 5 bit 0 0 1 6 bit 0 1 0 7 bit 0 1 1 8 bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9 bit UCTRL02 UART0 Control 2 Register E3H 7 6 5 4 3 2 1 0 UDRIE TXCIE RXCIE...

Page 136: ...ode 0 Normal operation 1 Loop Back mode 1 SS output to other slave device USBS Selects the length of stop bit 0 1 Stop Bit 1 2 Stop Bit TX8 The ninth bit of data frame Write this bit first before load...

Page 137: ...ic of UART and is auto cleared 0 No operation 1 Reset UART DOR This bit is set if a Data Overrun occurs While this bit is set the incoming data frame is ignored This flag is valid until the receive bu...

Page 138: ...Buffer and Receive Buffer share the same I O address with this DATA register The Transmit Data Buffer is the destination for data written to the UDATA register Reading the UDATA register returns the...

Page 139: ...5 0 0 191 0 0 103 0 2 207 0 2 191 0 0 4800 47 0 0 95 0 0 51 0 2 103 0 2 95 0 0 191 0 0 9600 23 0 0 47 0 0 25 0 2 51 0 2 47 0 0 95 0 0 14 4K 15 0 0 31 0 0 16 2 1 34 0 8 31 0 0 63 0 0 19 2K 11 0 0 23 0...

Page 140: ...18 Rev 1 8 76 8K 6 7 0 12 0 2 8 0 0 17 0 0 11 0 0 23 0 0 115 2 K 3 8 5 8 3 5 5 0 0 11 0 0 7 0 0 15 0 0 230 4 K 1 8 5 3 8 5 2 0 0 5 0 0 3 0 0 7 0 0 250K 1 0 0 3 0 0 2 7 8 5 7 8 3 7 8 6 5 3 0 5M 1 0 0 2...

Page 141: ...ith I 2 C bus standard Multi master operation Up to 400 KHz data transfer speed 7 bit address Support two slave addresses Both master and slave operation Bus busy detection 11 10 2 Block Diagram SDA F...

Page 142: ...ion A low to high transition on the SDA line while SCL is high defines a STOP P condition START and STOP conditions are always generated by the master The bus is considered to be busy after START cond...

Page 143: ...H by the slave And also when a slave addressed by a master is unable to receive more data bits the slave receiver must release the SDA line Data Packet The master can then generate either a STOP condi...

Page 144: ...test clock HIGH period A master may start a transfer only if the bus is free Two or more masters may generate a START condition Arbitration takes place on the SDA line while the SCL line is at the HIG...

Page 145: ...gure how to handle interrupt and ACK signal When the START bit is set 8 bit data in I2CDR is transmitted out according to the baud rate 6 This is ACK signal processing stage for address packet transmi...

Page 146: ...inues data transfer because slave can receive more data from master In this case load data to transmit to I2CDR 2 Master stops data transfer even if it receives ACK signal from slave In this case set...

Page 147: ...rrupt SCL line is held low Interrupt after stop command P Arbitration lost as master and addressed as slave LOST Other master continues Slave Receiver 0x1D or Transmitter 0x1F Master Receiver SLA W AC...

Page 148: ...iver go to appropriate section In this stage I 2 C holds the SCL LOW This is because to decide whether I 2 C continues serial transfer or stops communication The following steps continue assuming that...

Page 149: ...between master and slave is over To clear I2CSR write arbitrary value to I2CSR After this I 2 C enters idle state The processes described above for master receiver operation of I 2 C can be depicted...

Page 150: ...ndition Else if the address equals to SLA bits and the ACKEN bit is enabled I 2 C generates SSEL interrupt and the SCL line is held LOW Note that even if the address equals to SLA bits when the ACKEN...

Page 151: ...P Y N 0x46 P 0x22 IDLE IDLE Y GCALL 0x1F 0x97 0x17 From master to slave Master command or Data Write From slave to master 0xxx Value of Status Register ACK Interrupt SCL line is held low Interrupt aft...

Page 152: ...EN bit is enabled I 2 C generates SSEL interrupt and the SCL line is held LOW Note that even if the address equals to SLA bits when the ACKEN bit is disabled I 2 C enters idle state When SSEL interrup...

Page 153: ...Register I2CSAR A6H R W 00H I 2 C Slave Address Register I2CSAR1 A7H R W 00H I 2 C Slave Address Register 1 Table 11 18 Register map of I2C SLA W ACK DATA LOST S or Sr Y N 0x45 ACK STOP Y N 0x44 P 0x2...

Page 154: ...ctive 1 I 2 C is active RESET Initialize internal registers of I 2 C 0 No operation 1 Initialize I 2 C auto cleared INTEN Enable interrupt generation of I 2 C 0 Disable interrupt operates in polling m...

Page 155: ...ected Note 1 0 No STOP condition is detected 1 STOP condition is detected SSEL This bit is set when I 2 C is addressed by other master Note 1 0 I 2 C is not selected as slave 1 I 2 C is addressed by o...

Page 156: ...ting frequency of I 2 C in master mode fI2C is calculated by the following equation I2CSDAHR SDA Hold Time Register A3H 7 6 5 4 3 2 1 0 SDAH7 SDAH6 SDAH5 SDAH4 SDAH3 SDAH2 SDAH1 SDAH0 R W R W R W R W...

Page 157: ...ral call address or not when I 2 C operates in slave mode 0 Ignore general call address 1 Allow general call address I2CSAR1 I 2 C Slave Address Register 1 A7H 7 6 5 4 3 2 1 0 SLA17 SLA16 SLA15 SLA14...

Page 158: ...s Continuously Stop Stop BOD Enabled Disabled Enabled Main OSC 1 12MHz Oscillation Stop Stop INT RC OSC 12MHz Oscillation Stop Stop I O Port Retain Retain Retain or Input pull up mode Control Register...

Page 159: ...ed cause it has reset flags which are affected only by its specific reset source There re three kinds of reset sources which can be used to release STOP mode power on reset nPOR external reset P15 and...

Page 160: ...o check the external voltage level If the voltage level is higher than the BOD stop level VBODR the device wakes up normally to resume program execution Otherwise if the checked voltage level is below...

Page 161: ...tantaneously In BOD mode all analog and digital blocks except for BOD stops operating The internal state of the device is almost the same as in STOP mode But there are 3 different points as follows Fi...

Page 162: ...e disabled except BOD Each port type is redefined with P0PBC and P1PBC PxPBC bit is 1 input with pull up PcPBC bit is 0 user defined type is maintained Normal mode Reset mode All analog IPs are enable...

Page 163: ...sabled temporarily with chip BOD enable register BODR 0 is maintained Each port type is maintained with user defined type Current typ 1uA BOD mode All analog IPs are disabled except BOD BOD is enabled...

Page 164: ...3 BIT2 BIT1 BIT0 R W R W R W R W R W R W R W R W Initial value 00H SLEEP mode 01H Enters SLEEP mode STOP mode 03H Enters STOP mode NOTE 1 Write PCON register 01H or 03H to enter SLEEP or STOP mode 2 W...

Page 165: ...n a reset is asserted 13 2 Reset source Reset can be caused by a power on reset nPOR event configuration reset by software watchdog overflow voltage drop detection by BOD OCD command or by assertion o...

Page 166: ...reset pin P15 is ignored by the dedicated noise canceller To have an effect as a reset source P15 port should be maintained low continuously at least 8us of time TRNC in typical condition The TRNC may...

Page 167: ...eset XIN 2048 128KHz XIN 8MHz RESET_SYSB Config Read 250us X F2H about 30ms 250us X FFH about 32ms 00 01 02 03 04 05 06 00 01 02 03 00 01 02 F1 F2 F1 FE FF 00 01 02 03 External reset has no effect on...

Page 168: ...ue read point Rising section to reset release level 32ms after BODR or external reset is released Reset release point BIT overflow BIT is used to ensure oscillation stability time Normal operation Tab...

Page 169: ...ODR and the other is to indicate voltage levels above BOD stop level denoted by BODI0 1 2 3 4 each Remember that BOD itself does not generate a reset signal When operating voltage drops below a pre de...

Page 170: ...r DEBOUNCE CLK External VDD BODEN STOP MODE BODRF BOD Reset Flag CPU Write SCLK System CLK nPOR r Q CP STOP_OSCB VDD Rise VDC Lock s STOP_OSCB Indicates STOP mode active low signal VDC Lock VDC Lock d...

Page 171: ...RF BODRF BODLS1 BODLS0 BODEN R W R W R W R W R W R W R W R W Initial value C9H PORF Power on reset or software reset event NOTE 0 No POR event detected after clear 1 POR occurred EXTRF External Reset...

Page 172: ...ate is restored with BODEN 0 Disable BOD 1 Enable BOD NOTE To clear each reset flag write 0 to associated bit position Initial value of ocd mode debug mode is D9H BODSR BOD Status Register 8FH 7 6 5 4...

Page 173: ...n VBODI1 1 VDD dropped below VBODI1 CFGCR Configuration Control Register 8FH 7 6 5 4 3 2 1 0 SWRM STUE SWU SWR R W R W R W R W Initial value 10H SWRM The monitor of Software reset 0 Software reset was...

Page 174: ...er Access to All Internal Peripheral Units Internal data RAM Program Counter Non volatile Memories Extensive On chip Debug Support for Break Conditions Including Break Instruction Single Step Break Pr...

Page 175: ...When transmitter receives no acknowledge bit from the receiver error process is done by transmitter When acknowledge error is generated host PC issues a stop condition and re transmits the command Bac...

Page 176: ...MC96FR116C 176 November 2018 Rev 1 8 14 2 2 Packet transmission timing 14 2 2 1 Data transfer Figure 14 2 10 bit transmission packets Figure 14 3 Data transfer on the twin bus...

Page 177: ...ata output By receiver DSCL from master clock pulse for acknowledgement no acknowledge acknowledge data line stable data valid except Start and Stop change of data allowed DSDA DSCL St Sp START condit...

Page 178: ...t source for DSCL to fast 0 to 1 transition in high speed mode pull up resistors Rp Rp VDD DSCL IN DSDA IN DSCL IN DSDA IN Start wait start HIGH Host PC DSCL OUT Target Device DSCL OUT DSCL wait HIGH...

Page 179: ...be updated through registers setting ISP feature PROGRAM or ERASE operation is performed with single power supply Command interface for fast program and erase operation Up to 10 000 program erase cycl...

Page 180: ...cksum Register Low FSLBAx 2F61H 2F62H R W 00H F LASH Secure Lock Base Address Register FSLTAx 2F64H 2F65H R W 00H F LASH Secure Lock Top Address Register FSUBAx 2F67H 2F68H R W 00H F LASH Secure Unloc...

Page 181: ...program or erase Verify VFY 1 This bit initiates reading the entire FLASH area and must be set in chip test mode debugger mode or rom writing mode Clear all FARH FARM and FARL before setting this bit...

Page 182: ...H FARM and FARL registers are used for program erase or auto verify operation In program or erase mode these registers point to the page number to be programmed or erased FCR FLASH Control Register EC...

Page 183: ...ter is clocked by a clock which is divided by 64 from system clock XIN 64 It s a simple counter When program or erase operation starts the counter is cleared and start up counting until it reaches the...

Page 184: ...2 1 0 CSUM7 CSUM6 CSUM5 CSUM4 CSUM3 CSUM2 CSUM1 CSUM0 R R R R R R R R Initial value 00H CSUM 7 0 FLASH Read Checksum in auto verify mode In auto verify mode the FLASH address increases automatically b...

Page 185: ...SUBA13 FSUBA12 FSUBA11 FSUBA10 FSUBA9 FSUBA8 R W R W R W R W R W R W R W R W Initial value 00H FSUBA 15 8 Flash Secure Unlock Base Address FSUBA1 FLASH Secure Unlock Base Address 0 Register 2F68H 7 6...

Page 186: ...led LCTRL FLASH lock control 0 FLASH lock control is disabled 1 FLASH lock control is disabled FSLBAx FSLTAx FSUBAx FSUTAx and FSCTRL registers are used for code write protection If FSLBAx is 0x0100 F...

Page 187: ...n volatile memory 15 5 1 FLASH area division 15 5 2 Address configuration of FLASH memory 18 17 10 9 8 7 6 5 4 3 2 1 0 PAGE ADDRESS WORD ADDRESS FLASH Program 1FH 00H 00000H 03FFFH Page buffer size 32...

Page 188: ...0x05 Program 8 Wait PEVBSY bit in FESR EDH for OCD mode 9 ISP or Self Program Mode Exit FECR ECH 0x31 NOTE1 Program or Erase time is only to be set before real program or erase operation Normally the...

Page 189: ...1 Write AAH to 1555H 2 Write 55H to 1AAAH 3 Write A5H to 1555H NOTE 1 Refer to chapter 14 NOTE 2 Command sequence to activate FLASH program erase mode It is composed of sequential write to fixed FLAS...

Page 190: ...unsigned char pagerom FLASH_PBUFF_SIZE _at_ 0x8000 page buffer data unsigned char page_data FLASH_PBUFF_SIZE write data buffer void main unsigned p_index Step 2 flash_program_entry eeprom_page_erase 0...

Page 191: ...ration while FESR 7 0x00 void flash_page_write unsigned int addr unsigned char wdata int i unsigned char temp int addr_index Step 1 FETCR PGMTIME Step 3 page_buffer_reset Step 4 for i 0 I FLASH_PBUFF_...

Page 192: ...y mode after erase FLASH page buffer load Load data to page buffer Table 15 3 FLASH operating mode 15 7 Security The MC96FR116C provides one LOCKF bit to protect memory contents from illegal attempt t...

Page 193: ...ial value 00H BSIZE 1 0 Select Specific Area for Write Protection Boot Area Note When LOCKB 1 it is applied 00 512B 0000h 01FFh 01 1024B 0000h 03FFh 10 2048B 0000h 07FFh 11 4096B 0000h 0FFFh RSTDIS Se...

Page 194: ...Subtract immediate from A with borrow 2 1 94 INC A Increment A 1 1 04 INC Rn Increment register 1 1 08 0F INC dir Increment direct byte 2 1 05 INC Ri Increment indirect memory 1 1 06 07 DEC A Decremen...

Page 195: ...t byte 3 2 85 MOV dir Ri Move indirect memory to direct byte 2 2 86 87 MOV dir data Move immediate to direct byte 3 2 75 MOV Ri A Move A to indirect memory 1 1 F6 F7 MOV Ri dir Move direct byte to ind...

Page 196: ...2 2 70 CJNE A dir rel Compare A direct jne relative 3 2 B5 CJNE A d rel Compare A immediate jne relative 3 2 B4 CJNE Rn d rel Compare register immediate jne relative 3 2 B8 BF CJNE Ri d rel Compare i...

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