MC96FR116C
56
November, 2018 Rev.1.8
10.2 External Interrupt
The External Interrupts are triggered by the INT0, INT1, INT2, INT3 INT4 and INT5 pins. The External
Interrupts can be triggered by a falling or rising edge or a low or high level. The trigger mode and
trigger level is controlled by External Interrupt Edge Register (EIEDGEx) and External Interrupt
Polarity Register (EIPOLA). When the external interrupt is enabled and is configured as level triggered,
the interrupt will trigger as long as the pin is held low or high. External interrupts are detected
asynchronously. This implies that these interrupts can be used for wake-up sources from stop mode.
The interrupt requests from INT0, INT1, INT2, INT3, INT4 and INT5 pins can be monitored through
the External Interrupt Flag Register (EIFLAG).
2
2
2
2
EIFLAG1
INT1 Interrupt
EIFLAG0
INT0 Interrupt
EIFLAG3
INT3 Interrupt
EIFLAG2
INT2 Interrupt
EIEDGEx, EIPOLA
[AD
H
,AE
H
] EIEDGEx
[AF
H
] EIPOLA
INT0 Pin
(P00)
INT1 Pin
(P01)
INT2 Pin
(P02)
INT3 Pin
(P03)
2
2
EIFLAG5
INT5 Interrupt
EIFLAG4
INT4 Interrupt
INT4 Pin
(P04)
INT5 Pin
(P05)
Figure 10-1 External Interrupt trigger condition
