MC96FR116C
November, 2018 Rev.1.8
93
When T2H+T2L reaches to the value of T2DRH+T2DRL, an interrupt is requested if enabled. When
a compare-match occurs, the counter values T2H and T2L are captured into the capture registers
CDR2H and CDR2L respectively. At the same time, the counter is cleared to 0000
H
and starts up-
counting.
Bit 4 and 5 in EIEDGE (External Interrupt Edge Selection Register, AD
H
) register select the
triggering condition of external interrupt 2(INT2), a falling edge, a rising edge or both edge.
When Timer 2 operates in IR capture mode, the capture source becomes the output of IR AMP.
And the T2EDGE[1:0] bits in IRCC2 register select the triggering condition of Watch Timer output. In
this mode, Timer 2 detects the envelop of input carrier signal, and the T2IR bit in IRCC2 register
should be cleared to
‘0’
11.4.3.4 Carrier Counting Mode
Carrier Counting Mode is enabled by setting T2IR bit in IRCC2 register. This mode of operation is only
available when IRCEN bit in IRCC1 register is set. The clock source is the rising edge of input carrier
signal. Like output compare mode, when T2H+T2L reaches to the value of T2DRH+T2DRL, an
interrupt is requested if enabled.
The EC2E and CAP2 bit in T2CR register should be cleared to
‘0’ for proper operation.
11.4.3.5 Register Map
Name
Address
Dir
Default
Description
T2CR
C6
H
R/W
00
H
Timer 2 Mode Control Register
T2H
C7
H
R
00
H
Timer 2 Counter High
T2DRH
C7
H
W
FF
H
Timer 2 Data Register High
CDR2H
C7
H
R
00
H
Timer 2 Capture Data Register High
T2CR
0
X
0
X
X
X
X
X
ADDRESS : C6
H
INITIAL VALUE : 0000_0000
B
T2CN
IRSensor
[C7
H
]
T2IF
Timer2
Interrupt
16-bit Timer2 Counter
16-bit Timer2 Data Register
Clear
[C7
H
]
Comparator
T2ST
T2H
(8-bit)
T2L
(8-bit)
T2DRH
(8-bit)
T2DRL
(8-bit)
[CF
H
]
[CF
H
]
EC2E
T2_PE
T2CK2 T2CK1 T2CK0
T2CN
T2ST
IRCC2
X
1
X
X
X
X
X
X
ADDRESS : DF
H
INITIAL VALUE : 0000_0000
B
T3IR
T2IR
-
T3EDG
E1
T3EDG
E9
T2EDG
E1
T2EDG
E0
Figure 11-18 Block Diagram of Timer 2 in Carrier Counting Mode
