FLCTL_A Registers
562
SLAU356I – March 2015 – Revised June 2019
Copyright © 2015–2019, Texas Instruments Incorporated
Flash Controller A (FLCTL_A)
10.4.20 FLCTL_PRGBRST_DATA2_0 Register (offset = 080h)
Flash Program Burst Data2 Input Register (bits (32*(x+1)-1) downto 32*x) for (x = 0,1,2,3)
Figure 10-26. FLCTL_PRGBRST_DATA2_0 Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DATAIN
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATAIN
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
(1)
This bit field is writable
ONLY
when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the
bits will remain locked so as to not disrupt an operation that is in progress.
Table 10-32. FLCTL_PRGBRST_DATA2_0 Register Description
Bit
Field
Type
Reset
Description
31-0
DATAIN
(1)
RW
FFFF_FF
FFh
Program Burst 128 bit Data Word 2 (bits (32*(x+1)-1) downto 32*x) for (x =
0,1,2,3)
10.4.21 FLCTL_PRGBRST_DATA2_1 Register (offset = 084h)
Flash Program Burst Data2 Input Register (bits (32*(x+1)-1) downto 32*x) for (x = 0,1,2,3)
Figure 10-27. FLCTL_PRGBRST_DATA2_1 Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DATAIN
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATAIN
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
(1)
This bit field is writable
ONLY
when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the
bits will remain locked so as to not disrupt an operation that is in progress.
Table 10-33. FLCTL_PRGBRST_DATA2_1 Register Description
Bit
Field
Type
Reset
Description
31-0
DATAIN
(1)
RW
FFFF_FF
FFh
Program Burst 128 bit Data Word 2 (bits (32*(x+1)-1) downto 32*x) for (x =
0,1,2,3)