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Table 17.91. 0x0234 P3 Factional Division Enable
Reg Address
Bit Field
Type
Setting Name
Description
0x0234
3:0
R/W
P3_FRACN_MODE P3 (IN3) input divider fractional mode. Must be set to
0xB for proper operation.
0x0234
4
R/W
P3_FRAC_EN
P3 (IN3) input divider fractional enable
0: Integer-only division.
1: Fractional (or Integer) division.
Table 17.92. 0x0235-0x023A MXAXB Divider Numerator
Reg Address
Bit Field
Type
Setting Name
Description
0x0235
7:0
R/W
MXAXB_NUM
44-bit Integer Number
0x0236
15:8
R/W
MXAXB_NUM
0x0237
23:16
R/W
MXAXB_NUM
0x0238
31:24
R/W
MXAXB_NUM
0x0239
39:32
R/W
MXAXB_NUM
0x023A
43:40
R/W
MXAXB_NUM
Note that changing this register during operation may cause indefinite loss of lock unless the guidelines in are followed.
Table 17.93. 0x023B-0x023E MXAXB Divider Denominator
Reg Address
Bit Field
Type
Setting Name
Description
0x023B
7:0
R/W
MXAXB_DEN
32-bit Integer Number
0x023C
15:8
R/W
MXAXB_DEN
0x023D
23:16
R/W
MXAXB_DEN
0x023E
31:24
R/W
MXAXB_DEN
The M-divider numerator and denominator are set by ClockBuilder Pro for a given frequency plan. Note that changing this register dur-
ing operation may cause indefinite loss of lock unless the guidelines in are followed.
Table 17.94. 0x023F
Reg Address
Bit Field
Type
Setting Name
Description
0x023F
0
S
MXAXB_UPDATE The divider value for the XAXB input
Si5397/96 Reference Manual
Si5396 Register Map
silabs.com
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