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STATus Subsystem FSE
1065.6016.12
6.216
E-16
:STATus:OPERation:ENABle 0 to 65535
This command sets the bits of the ENABle section of the :STATus:QUEStionable register.
Example:
":STAT:OPER:ENAB 65535"
Features:
*RST value:
–
SCPI:
conforming
Modes:
A, VA, BTS, MS
The ENABle register selectively enables the individual events of the associated EVENt section for the
sum bit in the status byte.
:STATus:OPERation:PTRansition 0 to 65535
This command sets the edge detectors of all bits of the :STATus:OPERation register from 0 to 1 for
the transitions of the CONDition bit.
Example:
":STAT:OPER:PTR 65535"
Features:
*RST value:
–
SCPI:
conforming
Modes:
A, VA, BTS, MS
:STATus:OPERation:NTRansition 0 to 65535
This command sets the edge detectors of all bits of the :STATus:OPERation register from 1 to 0 for
the transitions of the CONDition bit.
Example:
":STAT:OPER:NTR 65535"
Features:
*RST value:
–
SCPI:
conforming
Modes:
A, VA, BTS, MS
:STATus:PRESet
This command resets the edge detectors and ENABle parts of all registers to a defined value. All
PTRansition parts are set to FFFFh, i.e., all transitions from 0 to 1 are detected. All NTRansition
parts are set to 0, i.e., a transition from 1 to 0 in a CONDition bit is not detected. The ENABle part of
the :STATus:OPERation and :STATus:QUEStionable registers are set to 0, i.e., all events in these
registers are not passed on.
Example:
":STAT:PRES"
Features:
*RST value:
–
SCPI:
conforming
Modes:
A, VA, BTS, MS
Содержание 1065.6000.20
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