Mindray Passport 5-Lead, Руководство по обслуживанию

Страница: 235 / 544

Passport 5-Lead, 5L, LT, XG Service Manual 0070-00-0420 2 - 33
Theory of Operation Block Diagrams
Sample and Hold
Sample and Hold consists of U13. The purpose of this circuit is to hold the signal at a
constant level, while the signal digitization is in progress. Sample and Hold is controlled
using the signal S/H according to below. Hold capacitor C35 is selected to provide
acquisition time 20 sec and droop rate 3mV/sec.
Comparator
Comparator is based on U14. It compares the signal held by sample and hold to the output
of the DAC. Output of the Comparator is a signal COMPOUT* (See). 63C09 processor
writes a value into the DAC and then checks the status of this signal. The procedure is
repeated until signal is digitized with the acceptable resolution.
Digital to Analog Converter (DAC)
Digital to Analog Converter consists of U20 and U21. 63C09 processor can access 12
digital inputs by writing into the control register. The analog output signal is connected to
input of sample and hold and subtraction input of Programmable Gain II block.
Interference Detector
Interference Detector monitors the output of Current to Voltage Preamp. U2A configured as a
comparator, which detects voltage levels more negative than -7.2 V. When this level is
detected
INTERF* line goes “low”. 63C09 CPU monitors this line to detect when Current to
Voltage Preamp is saturated.
Clock Generator
Clock Generator consists of 11.0592 MHz crystal oscillator Y1 and five D flip-flops U42,
U43, and U47. 11.0592 MHz OSC clock is divided in half by U47A, which outputs two
complementary clock signals:
SYSCLK
and
SYSCLK*
. These two clocks are used as a
baseline for digital section timing.
Parallel Interface
Parallel Interface consists of input buffers U31, U32, U33, and U34, output buffer/register
U35, and Q6. It’s function is to buffer the signals to/from ISA bus connector J1. Tri-state
signals of ISA address buffers U31 and U32 are controlled by the signal SROE, data input
buffer U34 is enabled by ISA-WR-OE*, and data output buffer/register is enabled by ISA-RD-
OE* and clocked by ISA-RD-CK*. All of these signals are generated by ISA Bus Interface.
ISA Bus Interface
ISA Bus Interface performs several distinct functions:
• ISA Bus Address Decoder
Address decoder section of ISA Bus Interface generates SRAM control signals (SRCE* and
SRWR*) and 63C09 processor signals HALT*, CLR*, and FIRQ*. SRAM signals are derived
from inputs SA16 through SA19 according to timing relationship described later in the
document. 63C09 signals are asynchronously set (disabled) when a valid write cycle is
detected and reset (enabled) during the read cycle.