Mindray Passport 5-Lead, Руководство по обслуживанию

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Block Diagrams Theory of Operation
2 - 30 0070-00-0420 Passport 5-Lead, 5L, LT, XG Service Manual
ISA bus processor can control 63C09 operations by accessing CLR* (63C09 reset), HALT*
(6309 halt), and FIRQ* (63C09 fast interrupt request) signals. These signals are set by
writing to an assigned address location and reset by reading from the same location (See ).
Although hardware assures proper powerup conditions of these signals, they should still be
initialized by external processor software.
Control Register
Control Register consist of three 74C374 octal D flip flops (U17, U18, and U19). When
data is written into corresponding memory address space one of three strobe signals
(APOUT0, APOUT1, or APOUT3) is activated and data is latched to the output control
signals. Only 63C09 processor can access the control register. Table II, and Table III show
how data lines are mapped to the control register outputs.
STROBE NAME APOUT0
INPUT OUTPUT DESTINATION
D0 DIAG Demultiplexer
D1 RUN/CAL* Sequencer, Current to Voltage Preamp
D2 IR0 Sequencer (CV Preamp Intrared Gain)
D3 IR1 Sequencer (CV Preamp Intrared Gain)
D4 RED0 Sequencer (CV Preamp Red Gain)
D5 RED1 Sequencer (CV Preamp Red Gain)
D6 S/H Sample and Hold
D7 CHNLMUX Remultiplexer
STOBE NAME APOUT1
INPUT OUTPUT DESTINATION
D0 BIT 12 (LSB) DAC Bit 0
D1 BIT 11 DAC Bit 1
D2 BIT 10 DAC Bit 1
D3 BIT 9 DAC Bit 1
D4 BIT 8 DAC Bit 1
D5 BIT 7 DAC Bit 1
D6 BIT 6 DAC Bit 1
D7 BIT 5 DAC Bit 1
STOBE NAME APOUT2
INPUT OUTPUT DESTINATION
D0 BIT 4 DAC Bit 8
D1 BIT 3 DAC Bit 9
D2 BIT 2 DAC Bit 10
D3 BIT 1 DAC Bit 11
D4 ACG0 AC GAIN
D5 ACG1 AC GAIN