Mindray Passport 5-Lead, Руководство по обслуживанию

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Passport 5-Lead, 5L, LT, XG Service Manual 0070-00-0420 2 - 41
Theory of Operation Block Diagrams
CPU
Device U1 is an MC68302, which contains a 68000 core CPU and much of the peripherals
used in the Passport PCM board. The CPU contains a 24-bit address bus and a 16-bit data
bus. Along with Y1, and a resistor/capacitor network, U1 shall operate at a clock speed of
16.5888MHz. This clock rate is the highest clock rate that the MC68302 can operate while
being a multiple of the baud rate of 115.2Khz for Front End communications.
There are 4 programmable chip select/wait state control groups. They are listed in below.
Datasette
The Datasette provides program memory and data storage for the main CPU module in the
Passport.
The Datasette contains two 512Kx8 FLASH ROM ICs and two 128Kx8 Static RAM ICs. They
are accessed by the host CPU via two chip select lines; even (CSL*) and odd (CSH*). Both of
these chip select signals should be decoded for the first 4 megabyte of the host’s memory
address space. The host module must decode the A0 address line to generate the even and
odd chip selects. Further decoding is provided by U5. The address space which is allocated
by the host CPU module consists of 2x2 megabyte regions. The first region (000000-
0x1FFFFF) is allocated for ROM use. Only one megabyte of FLASH ROM is used, therefore
the ROM is mirrored in the first and second megabyte of the address space. The upper 2
megabyte region (0x200000-03FFFFF) can be subdivided into 8x256K or 4x512K regions.
The 256K of RAM on the Datasette is decoded to respond in the upper half of each of the
512K regions.
A jumper, J1 has been added to the module to allow for use in a commercial PROM
programmer. Most PROM programmers have the capability of obtaining manufacturer and
device IDs from the device. This is possible by applying a higher than normal voltage at the
input address pin, A9. This voltage may be alright for the FLASH ROMs on the Datasette, but
it will cause damage to the static RAMs on the Datasette. To prevent this possible damage
from occuring the jumper J1 was added. When J1 is installed the address signal A10 is
connected to the A9 input pin of the SRAMs. This is necessary when the Datasette is
operating inside a Passport. This jumper must be removed if the Datasette is to be used in a
PROM programmer.
The CPU module operating at 16.5888Mhz will necessitate the use of 1 wait state to access
SRAM and 0 wait states to access FLASH ROM.
CHIP SELECT GROUP DESCRIPTION WAIT STATES
CS0 ROM 1
CS1 NON-VOLATILE RAM 1
CS2 VIDEO RAM EXTERNAL SELECT
CS3 PERIPHERALS 3