GE H
EALTHCARE
D
IRECTION
FC091194, R
EVISION
11
V
IVID
7 S
ERVICE
M
ANUAL
Chapter 5 - Components and Functions (Theory)
5 - 87
5-4-5-12
BEP1 Block Diagram
Figure 5-56 CPU/Back-End Processor Block Diagram (BEP1)
OP T IO NA L S C S I C A R D
SLOT 5
UNU S E D S L OT
SLOT 3
A G P V IDE O
SLOT 2
SLOT 7
10/100bT
PARALLEL
COM1
COM2 (EXT)
USB1
USB2
P C MOT HE R B O A R D
P C IO MODUL E
AT
X
P
O
W
E
R
S
U
P
P
LY
UP
S
HA R D DR IV E
E C G
O P T IONA L MOD
C D R W
ID
E
#
2
JW
R
1
SLOT 4
PC2IP
RS232 #3
RS232 #4
I2C
P C 2IP
SLOT 6
AC P
O
W
ER
RS422
RGB OUT
JFP1
SVGA OUT 1
SVGA OUT 2
S/C VIDEO OUT
SVGA IN
POWER
UNUS E D S L OT
F ront P anel
E T HE R NE T
P C 2IO B o
ard
P C V IC B oard
HD L ed
ID
E #
1
UP S B attery
SLOT 1
Control
MIDDLE DRIVE BAY
BOTTOM DRIVE BAY
INTERNAL DRIVE BAY
TOP DRIVE BAY
C P U #1
C P U #2
2
5
6 MB
DIMM
25
6 M
B
D
IM
M
DI
MM
S
lot
#1
D
IM
M
Slot
#2
D
IM
M
Slot
#3
D
IM
M
Slot
#4
JWOL1
AG P S lot
P C I S lo t #1
P C I S lo t #2
P C I S lo t #3
P C I S lo t #4
P C I S lo t #5
JC
D1
25
6 MB
D
IM
M
Содержание Vivid 7
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