Freescale Semiconductor e200z3, Справочное руководство

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Register Model
e200z3 Power Architecture Core Reference Manual, Rev. 2
2-16 Freescale Semiconductor
LR contents are read into a GPR using mfspr. The contents of a GPR can be written to LR using mtspr.
LR[62–63] are ignored by bclr instructions.
2.7 SPE and SPFP APU Registers
The SPE and SPFP include the signal processing and embedded floating-point status and control register
(SPEFSCR). The SPE implements a 64-bit accumulator that is described in
Section 2.7.2, “Accumulator
(ACC).”
2.7.1 Signal Processing/Embedded Floating-Point Status and Control
Register (SPEFSCR)
SPEFSCR, shown in Figure 2-10 , is used for status and control of SPE and embedded floating-point
instructions.
32 63
Field Link address
Reset Undefined on m_por assertion, unchanged on p_reset_b assertion
R/W R/W
SPR SPR 8
Figure 2-9. Link Register (LR)
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Field SOVH OVH FGH FXH FINVH FDBZH FUNFH FOVFH — FINXS FINVS FDBZS FUNFS FOVFS MODE
Reset 0000_0000_0000_0000
R/W R/W
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Field SOV OV FG FX FINV FDBZ FUNF FOVF — FINXE FINVE FDBZE FUNFE FOVFE FRMC
Reset 0000_0000_0000_0000
R/W R/W
SPR SPR 512
Figure 2-10. Signal Processing and Embedded Floating-Point Status and Control
Register (SPEFSCR)
High-Word Error Bits
Status Bits
Enable Bits