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Instruction Pipeline and Execution Timing
e200z3 Power Architecture Core Reference Manual, Rev. 2
6-12 Freescale Semiconductor
Figure 6-14. mtspr, mfspr Instruction Execution—(1)
Figure 6-15 applies to the mtmsr, wrtee, and wrteei instructions. Execution of subsequent instructions
stalls until these instructions writeback.
Figure 6-15. mtmysr, wrtee, wrteei Instruction Execution
Access to MMU SPRs stalls until all outstanding bus accesses complete and the MMU is idle
(p_[i,d]_cmbusy negated) to allow an access window where no translations or cache cycles are required.
Figure 6-16 shows an example where an outstanding bus access delays mtspr/mfspr execution until the
bus becomes idle. Processor access requests are held off during execution of an MMU SPR instruction. A
subsequent access request may be generated in the WB cycle. This same protocol applies to MMU
management instructions (such as tlbre, tlbwe, etc.) as well as to the DCRs.
Time Slot
mtspr , mfspr
DEC EXE1 IFETCH WB
Previous Instruction (Multicycle)
DEC EXE IFETCH WB
DEC Stall IFETCH EXE WB
Next Instruction
EXEn
. . .
. . .
. . .
Stall
Stall
Time Slot
mtmsr , wrtee , wrteei
DEC EXE IFETCH
Previous Instruction
DEC EXE IFETCH WB
DEC Stall IFETCH EXE
WB
Next Instruction
WB