Freescale Semiconductor e200z3, Справочное руководство, Страница: 293 / 442

External Core Complex Interfaces
e200z3 Power Architecture Core Reference Manual, Rev. 2
Freescale Semiconductor 7-25
Table 7-20 lists interface signals that assist in implementing a real-time development tool capability with
a controller that is external to the
core
. These signals are described in Section 10.11, “Nexus3/ Pin
Interface.”
Table 7-21 lists the primary JTAG interface signals. These signals are usually connected directly to device
pins (except for j_tdo, which needs tri-state and edge support logic), unless JTAG TAP controllers are
concatenated.
Table 7-22 describes JTAG interface signals.
Table 7-20. core Development Support (Nexus3) Signals
Signal Type Description
nex_mcko O Nexus3 clock output
nex_rdy_b O Nexus3 ready output
nex_evto_b O Nexus3 event-out output
nex_evti_b I Nexus3 event-in input
nex_mdo[n:0] O Nexus3 message data output
nex_mseo_b[1:0] O Nexus3 message start/end output
Table 7-21. JTAG Primary Interface Signals
Signal Name Type Description
j_trst_b I JTAG test reset
j_tclk I JTAG test clock
j_tms I JTAG test mode select
j_tdi I JTAG test data input
j_tdo O Test data out to master controller or pad
j_tdo_en O Enables TDO output buffer. j_tdo_en is asserted when the
TAP controller is in the shift_dr or shift_ir state.
Table 7-22. Descriptions of JTAG Interface Signals
Signal I/O Signal Description
j_tdi I JTAG/OnCE serial input. Provides data and commands to the OnCE controller. Data is latched on the
rising edge of
j_tclk. Data is shifted into the OnCE serial port lsb first.
j_tclk I JTAG/OnCE serial clock. Supplies the serial clock to the OnCE control block. The serial clock provides
pulses required to shift data and commands into and out of the OnCE serial port (data is clocked into
the OnCE on the rising edge and is clocked out of the OnCE serial port on the rising edge). The debug
serial clock frequency must not exceed 50% of the processor clock frequency.