Instruction Model
e200z3 Power Architecture Core Reference Manual, Rev. 2
Freescale Semiconductor
3-19
X
011111
10110 01010 0
addzeo
Add to Zero Extended with CA & record OV
X
011111
10110 01010 1
addzeo.
Add to Zero Extended with CA & record OV & CR
X
011111
00000 11100 0
and
AND
X
011111
00000 11100 1
and.
AND & record CR
X
011111
00001 11100 0
andc
AND with Complement
X
011111
00001 11100 1
andc.
AND with Complement & record CR
D
011100
––––– ––––– –
andi.
AND Immediate and record CR
D
011101
––––– ––––– –
andis.
AND Immediate Shifted and record CR
I
010010
––––– ––––0 0
b
Branch
I
010010
––––– ––––1 0
ba
Branch Absolute
B
010000
––––– ––––0 0
bc
Branch Conditional
B
010000
––––– ––––1 0
bca
Branch Conditional Absolute
XL
010011
10000 10000 0
bcctr
Branch Conditional to Count Register
XL
010011
10000 10000 1
bcctrl
Branch Conditional to Count Register and Link
B
010000
––––– ––––0 1
bcl
Branch Conditional and Link
B
010000
––––– ––––1 1
bcla
Branch Conditional and Link Absolute
XL
010011
00000 10000 0
bclr
Branch Conditional to Link Register
XL
010011
00000 10000 1
bclrl
Branch Conditional to Link Register and Link
I
010010
––––– ––––0 1
bl
Branch and Link
I
010010
––––– ––––1 1
bla
Branch and Link Absolute
X
011111
00000 00000 /
cmp
Compare
D
001011
––––– ––––– –
cmpi
Compare Immediate
X
011111
00001 00000 /
cmpl
Compare Logical
D
001010
––––– ––––– –
cmpli
Compare Logical Immediate
X
011111
00000 11010 0
cntlzw
Count Leading Zeros Word
X
011111
00000 11010 1
cntlzw.
Count Leading Zeros Word and record CR
XL
010011
01000 00001 /
crand
Condition Register AND
XL
010011
00100 00001 /
crandc
Condition Register AND with Complement
Table 3-11. Instructions Sorted by Mnemonic (continued)
Format
Opcode
Mnemonic
Instruction
Primary
(Inst
0:5
)
Extended
(Inst
21:31
)
Legend:
-
Don’t care, usually part of an operand field
/
Reserved bit, invalid instruction form if encoded as 1
?
Allocated for implementation-dependent use.
Содержание e200z3
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