Freescale Semiconductor e200z3, Справочное руководство, Страница: 272 / 442

External Core Complex Interfaces
e200z3 Power Architecture Core Reference Manual, Rev. 2
7-4 Freescale Semiconductor
Table 7-1 shows core signal function and type, signal definition, and reset value. Signals are presented in
functional groups.
Table 7-1. Interface Signal Definitions
Signal Name I/O Reset Definition
Clock and Signals Related to Reset
m_clk I Global system clock
m_por I Power-on reset
p_reset_b I Processor reset input
p_resetout_b O Processor reset output
p_rstbase[0:19] I Reset exception handler base address, value to be loaded into TLB entry 0 on reset.
p_rst_endmode I Reset endian mode select, value to be loaded into TLB entry 0 on reset.
p_rst_vlemode I Reset VLE mode select, value to be loaded into TLB entry 0 on reset.
Memory Interface Signals
p_i_hmaster[3:0],
p_d_hmaster[3:0] O — Master ID
p_i_haddr[31:0],
p_d_haddr[31:0] O — Address bus
p_i_hwrite, p_d_hwrite O 0 Write signal (always driven low for p_i_hwrite)
p_i_hprot[5:0],
p_d_hprot[5:0] O — Protection codes
p_i_htrans[1:0],
p_d_htrans[1:0] O — Transfer type
p_i_hburst[2:0] ,
p_d_hburst[2:0]
O — Burst type
p_i_hsize[1:0],
p_d_hsize[1:0] O — Transfer size
p_i_hunalign,
p_d_hunalign O — Indicates that the current data access is misaligned
p_i_hbstrb[7:0] ,
p_d_hbstrb[7:0]
O 0 Byte strobes
p_i_hrdata[63:0],
p_d_hrdata[63:0]
I Read data bus
p_d_hwdata[63:0] O — Write data bus
p_i_hready,
p_d_hready
I Transfer ready
p_i_hresp[2:0],
p_d_hresp[2:0] I Transfer response
Master ID Configuration Signals