Freescale Semiconductor e200z3, Справочное руководство

Страница: 331 / 442

Power Management
e200z3 Power Architecture Core Reference Manual, Rev. 2
Freescale Semiconductor 8-3
8.1.2 Power Management Control Bits
Software uses the register fields listed in Table 8-3 to generate a request to enter a power-saving state and
to choose the state to be entered.
8.1.3 Software Considerations for Power Management
Setting MSR[WE] generates a request to enter a power-saving state (doze, nap, or sleep). This state must
be previously determined by setting the appropriate HID0 bit. Setting MSR[WE] does not directly affect
execution, but is reflected on p_doze, p_nap, and p_sleep, depending on the setting of the HID0 DOZE,
NAP, and SLEEP bits. Note that the core is not affected by assertion of these signals directly. External
system hardware may interpret the state of these signals and activate the p_halt and/or p_stop inputs to
cause the core to enter a quiescent state, in which clocks may be disabled for low-power operation.
To ensure a clean transition into and out of a power-saving mode, the following program sequence is
recommended:
sync
mtmsr (WE)
isync
loop: br loop
An interrupt is typically used to exit a power-saving state. The p_wakeup output is used to indicate to the
system logic that an interrupt (or a debug request) has become pending. System logic uses this output to
re-enable the clocks and exit a low-power state. The interrupt handler is responsible for determining how
to exit the low-power loop if one is used. The vectored interrupt capability provided by the core may help
determine whether an external hardware interrupt is used to perform the wake-up.
8.1.4 Debug Considerations for Power Management
When a debug request is presented to the core when it is in either the halted or stopped state, p_wakeup is
asserted, and when m_clk is provided to the CPU, it temporarily exits the halted or stopped state and enters
debug mode, regardless of the assertion of p_halt or p_stop. The p_halted and p_stopped outputs are
negated as long as the CPU remains in a debug session (jd_debug_b asserted). When the debug session is
exited, the CPU resamples the p_halt and p_stop inputs and re-enters halted or stopped state as appropriate.
Table 8-3. Power Management Control Bits
Bit Description
MSR[WE] Used to qualify assertion of the p_doze, p_nap, and p_sleep outputs to the integrated logic. When MSR[WE]
is negated, these signals are negated. If MSR[WE] is set, these pins reflect the state of their respective HID0
control bits.
HID0[DOZE] The interpretation of the DOZE mode bit is done by the external integrated logic. Doze mode on the core is
intended to be the halted state with the clocks running.
HID0[NAP] The interpretation of the NAP mode bit is done by the external integrated logic. Nap mode on the core may be
used for a power-down state with the time base enabled.
HID0[SLEEP] The interpretation of the SLEEP mode bit is done by the external integrated logic. Sleep mode on the core may
be used for a power-down state with the time base disabled.