Freescale Semiconductor e200z3, Справочное руководство

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External Core Complex Interfaces
e200z3 Power Architecture Core Reference Manual, Rev. 2
7-30 Freescale Semiconductor
7.4 Internal Signals
Table 7-26 lists internal signals that are mentioned in this manual. These signals are not directly accessible
to the user, but are used in this document to help describe the general behavior of the core.
7.5 Timing Diagrams
The following sections discuss various types of timing diagrams.
7.5.1 Processor Instruction/Data Transfers
Transfer of data between the core and peripherals involves the address bus, data buses, and control and
attribute signals. The address and data buses are parallel, non-multiplexed buses, supporting byte, half
word, 3-byte, word, and double-word transfers. All bus inputs and outputs are sampled and driven with
respect to the rising edge of m_clk. The core moves data on the bus by issuing control signals and using a
handshake protocol to ensure correct data movement.
The memory interface operates in a pipelined fashion to allow additional access time for memory and
peripherals. AHB transfers consist of an address phase that lasts only one cycle, followed by the data phase
that may last for one or more cycles, depending on the state of p_[d,i]_hready.
Read transfers consist of the following:
• A request cycle, where address and attributes are driven along with a transfer request
• One or more memory access cycles to perform accesses and return data to the CPU for alignment,
sign or zero extension, and forwarding.
Table 7-26. Internal Signal Descriptions
Signal Name Description
p_addr[0:31] Address bus. Provides the address for a bus transfer.
p_ta_b Transfer acknowledge. Indicates completion of a requested data transfer operation. An external device asserts
p_ta_b to terminate the transfer. For the core to accept the transfer as successful, p_tea_b must remain high
while
p_ta_b is asserted.
p_tea_b Transfer error acknowledge. Indicates that a transfer error condition has occurred and causes the core to
immediately terminate the transfer. An external device asserts
p_tea_b to terminate the transfer with error.
p_tea_b has higher priority than p_ta_b.
p_treq_b Transfer request. The core drives this output to indicate that a new access has been requested.
p_xfail_b Store exclusive failure. An external agent causes assertion of p_xfail_b to indicate a failure of the store portion
of an stwcx. for the current transfer. p_xfail_b is ignored if p_tea_b is asserted, because the store terminated
with an error.
Assertion of
p_xfail_b with p_ta_b does not cause an exception; it indicates that the store was not performed
due to a loss of reservation (determined by an external agent). The CPU updates the condition code accordingly
and clears any outstanding reservation.
p_xfail_b may be asserted by reservation logic or as a result of a system
bus transfer with a failure response that is passed back to the CPU from the BIU. The AMBA XFAIL response
is signaled back to the CPU using this signal. See
Section 3.7, “Memory Synchronization and Reservation
Instructions.” p_xfail_b is ignored for all transfers other than an stwcx. .