Freescale Semiconductor e200z3, Справочное руководство

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Instruction Pipeline and Execution Timing
e200z3 Power Architecture Core Reference Manual, Rev. 2
Freescale Semiconductor 6-17
Table 6-3 shows detailed timing for each instruction mnemonic along with serialization requirements. As
this table shows, the VLE instructions have the same latencies and serialization as their equivalents in the
PowerPC architecture. Those instructions are listed by their root mnemonic.
Table 6-2. Instruction Class Cycle Counts
Class of Instructions Latency Throughput Special Notes
Integer: add , sub , shift , rotate , logical , cntlzw 1 1
Integer: compare 1 1
Branch 2/1 2/1 Branches take between 1 and 2 cycles to
execute.
Multiply 1 1
Divide 6–16 6–16 Data dependent timing
CR logical 1 1
Loads (non-multiple) 1 1
Load multiple 1 + n/2 (max) 1 + n/2 (max) Timing depends on n and address alignment.
Stores (non-multiple) 1 1
Store multiple 1 + n/2 (max) 1 + n/2 (max) Timing depends on n and address alignment.
mtmsr , wrtee , wrteei 2& 2
mcrf 1 1
mfspr , mtspr 2& 2& Applies to debug SPRs, optional unit SPRs
mfspr , mfmsr 1 1 Applies to internal, non-debug SPRs
mfcr , mtcr 1 1
rfi , rfci , rfdi 3 -
sc 3 -
tw , twi 3 - Trap taken timing
Table 6-3. Instruction Timing by Mnemonic
Mnemonic Latency Serialization Comments
addc [ o ][ . ] 1 None
adde [ o ][ . ] 1 None
addi , e_addi [ . ], e_add16i , e_add2i. , se_addi 1 None
addic [ . ], e_addic[.] 1 None
addis , e_add2is 1 None
addme [ o ][ . ] 1 None
addze [ o ][ . ] 1 None
add [ o ][ . ], se_add 1 None
andc [ . ], se_andc 1 None