Freescale Semiconductor e200z3, Справочное руководство

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Register Model
e200z3 Power Architecture Core Reference Manual, Rev. 2
2-68 Freescale Semiconductor
MAS3 fields are defined in Table 2-35 .
The MAS4 register, shown in Figure 2-51 , contains fields for specifying default information to be
pre-loaded on certain MMU related exceptions.
The MAS4 fields are defined in Table 2-36 .
Table 2-35. MAS3—RPN and Access Control
Bits Name Description
32–51 RPN Real page number.
Only bits that correspond to a page number are valid. Bits that represent offsets within a page are ignored
and should be zero.
52–53 — Reserved, should be cleared.
54–57 U0–U3 User bits.
58–63 PERMIS Permission bits (UX, SX, UW, SW, UR, SR).
SPR 628 Access: Supervisor read/write
32 33 34 35 36 39 40 47 48 51 52 55 56 57 58 59 60 61 62 63
R
— TLBSELD — TIDSELD — TSIZED — VLED WD ID MD GD ED
W
Reset All zeros
Figure 2-51. MMU Assist Register 4 (MAS4)
Table 2-36. MAS4—Hardware Replacement Assist Configuration Register
Bits Name Description
32–33 — Reserved, should be cleared.
34–35 TLBSELD Default TLB selected.
01 TLB1 (ignored by the e200z3, should be written to 01 for future compatibility)
36–43 — Reserved, should be cleared.
44–47 TIDSELD TID default selection value. 4-bit field that specifies which of the current PID registers should be used to
load the MAS1[TID] field on a TLB miss exception.
The PID registers are addressed as follows:
0000 = PID0 (PID).
0001 = PID1.
...
1110 = PID14.
A value that references a non-implemented PID register causes a value of 0 to be placed in MAS1[TID].
48–51 — Reserved, should be cleared.
52–55 TSIZED Default TSIZE value.
56–57 — Reserved, should be cleared.
58 VLED Default VLE value. Specifies the default value loaded into MAS2[VLE] on a TLB miss exception.
59–63 DWIMGE Default WIMGE values.