Compaq ES40CSLP, Инструкция по установке, использованию и обслуживанию

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Operation
3–2 Compaq ES40CSLP Rackmount System Installation/User/Service Guide
3.3 Power-Up Displays
Power-up information is displayed on the OCP and the system's console terminal. If the SRM
console environment variable is set to serial, the entire power-up display, consisting of the
SROM and SRM power-up messages, is printed on the VT terminal screen. If console is set to
graphics, no SROM messages are displayed, and the SRM messages are delayed until VGA
initialization has been completed.
3.3.1 SROM Power-Up Display
SROM code is executed first. Example 3-1 shows the SROM power-up messages and
corresponding operator control panel messages. Example 3-2 shows the messages that are
displayed once the SROM has transferred control to the SRM console. For a list of SROM
power-up status , see Table 3-1.
Example 3-1 Sample SROM Power-Up Display
SROM Power-Up Display OCP Message
™
SROM V1.00 CPU #00 @ 0500 MHz
SROM program starting
š
Reloading SROM
SROM V1.00-F CPU # 00 @ 0500 MHz
SROM program starting
Starting secondary on CPU #1
›
Starting secondary on CPU #2
Starting secondary on CPU #3
Bcache data tests in progress
œ
Bcache address test in progress
CPU parity and ECC detection in progress
Bcache ECC data tests in progress
Bcache TAG lines tests in progress
Memory sizing in progress

Memory configuration in progress
Memory data test in progress
Memory address test in progress
Memory pattern test in progress
Memory thrashing test in progress
Memory initialization
Loading console
Code execution complete (transfer control)
ž
PCI Test
Power on
RelCPU
BC Data
Size Mem
Load ROM
Jump to Console
™
When the system is powered up, the serial SROM code is loaded into the I-cache on the
first available CPU, which becomes the primary CPU. The order of precedence is CPU0,
CPU1, and so on. The primary CPU attempts to access the PCI bus. If it cannot, either a
hang or a failure occurs and this is the only message displayed.
š
The primary CPU interrogates the I
2
C EEROM on the system motherboard and CPU
modules through shared RAM. The primary CPU determines the CPU and system
configuration to jump to.
The primary CPU next checks the SROM checksum to determine the validity of the
Flash SROM sectors.
If Flash SROM is invalid, the primary CPU reports the error and continues the execution
of the serial SROM code. The invalid Flash SROM must be reprogrammed.
If Flash SROM is good, the primary CPU programs the appropriate registers with the
values from the Flash data and selects itself as a target CPU to be loaded.