AT32F435/437
Series Reference Manual
2022.11.11
Page 366
Rev 2.03
Figure 18-12 Data alignment
SIGN
SIGN
SIGN
SIGN
DT[11] DT[10]
DT[9]
DT[8]
DT[7]
DT[6]
DT[5]
DT[4]
DT[3]
DT[2]
DT[1]
DT[0]
SIGN
SIGN
SIGN
SIGN
DT[5]
DT[4]
DT[3]
DT[2]
DT[1]
DT[0]
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN DT[11] DT[10]
DT[9]
DT[8]
DT[7]
DT[6]
DT[5]
DT[4]
DT[3]
DT[2]
DT[1]
DT[0]
0
0
0
SIGN
SIGN
SIGN
SIGN
DT[5]
DT[4]
DT[3]
DT[2]
DT[1]
DT[0]
SIGN
SIGN
SIGN
SIGN
SIGN
0
0
0
0
0
DT[11] DT[10]
DT[9]
DT[8]
DT[7]
DT[6]
DT[5]
DT[4]
DT[3]
DT[2]
DT[1]
DT[0]
DT[11] DT[10]
DT[9]
DT[8]
DT[7]
DT[6]
DT[5]
DT[4]
DT[3]
DT[2]
DT[1]
DT[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DT[5]
DT[4]
DT[3]
DT[2]
DT[1]
DT[0]
DT[5]
DT[4]
DT[3]
DT[2]
DT[1]
DT[0]
0
0
0
0
0
0
0
0
0
0
Preempted channel data 12 bits
Right-alignment
Ordinary channel data 12 bits
Ordinary channel data 6 bits
Right-alignment
Right-alignment
Right-alignment
Left-alignment
Left-alignment
Left-alignment
Left-alignment
Preempted channel data 6 bits
18.4.6.2 Data read
Read access to the ADC_ODT register using CPU or DMA gets the converted data of the ordinary group.
Read access to the ADC_PDTx register using CPU gets the converted data of the preempted group.
The EOCSFEN bit in the ADC_CTRL2 register can be used to select when to set the ordinary group
conversion complete flag, that is, at the end of sequence mode or each time the ordinary data register
is updated.
When the OCDMAEN bit is set in the ADC_CTRL2 register, the ADC will issue DMA requests each time
the ADC_OTD register is updated.
When the EOCSFEN or OCDMAEN is set, the ADC will automatically start overflow detection. If an
overflow event occurs, the OCCO flag will be set, the ADC stops conversion, and the last valid data is
stored in the data register. If the DMA is used, the DMA request remains set so that the DMA can read
the last valid data. The OCCO flag is cleared by software, and the ADC is triggered again so that it starts
conversion from the next channel of the valid data. In this case, even if an overflow event occurs halfway,
all the data read are valid and in order.
The OCDRCEN bit in the ADC_CTRL2 register can be used to select whether to continually send DMA
requests after the DMA transfer register is reset.
18.4.7 Voltage monitoring
The OCVMEN bit or PCVMEN bit in the ADC_CTRL1 register is used to enable voltage monitoring based
on the converted data.
The VMOR bit will be set if the converted result is outside the high threshold (ADC_VMHB register) or
is less than the low threshold (ADC_VMLB register).
The VMSGEN bit in the ADC_CTRL1 register is used to enable voltage monitor on either a single
channel or all the channels. The VMCSEL bit is used to select a specific channel that requires voltage
monitoring.
Voltage monitoring is based on the comparison result between the original converted data and the 12-
bit voltage monitor boundary register, irrespective of the CRSEL, PCDTOx and DTALIGN bits.
When using an oversampler, voltage monitoring is based on the comparison result between the 16-bit
registers (ADC_VMHB[15:0] and ADC_VMLB[15:0]) and the oversampled data.
