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AT32F435/437
Series Reference Manual
2022.11.11
Page 254
Rev 2.03
polarity (ESP in TMRx_STCTRL register), external signal frequency division (ESDIV[1:0] in
TMRx_STCTRL) and external signal filter (ESF[3:0] in TMRx_STCTRL register).
-
Set TRGIN signal source using the STIS[1:0] bit in TMRx_STCTRL register
-
Enable external clock mode A by setting SMSEL=3
’b111 in TMRx_STCTR register
-
Set counting frequency through the DIV[15:0] in TMRx_DIV register
-
Set counting period through the PR[15:0] in TMRx_PR register
-
Enable counter through the TMREN bit in TMRx_CTRL1 register
To use external clock mode B, follow the steps below:
-
Set external signal polarity through the ESP bit in TMRx_STCTRL register
-
Set external signal frequency division through the ESDIV[1:0] bit in TMRx_STCTRL register
-
Set external signal filter through the ESF[3:0] bit in TMRx_STCTRL register
-
Enable external clock mode B through the ECMBEN bit in TMRx_STCTR register
-
Set counting frequency through the DIV[15:0] bit in TMRx_DIV register
-
Set counting period through the PR[15:0] bit in TMRx_PR register
-
Enable counter through the TMREN in TMRx_CTRL1 register
Figure 14-10 Block diagram of external clock mode A
TMRx_EXT
ESF
filter
EXT
C1INC
C1IFP1
C2IPF2
TMRx_CH2
C2DF
C2P/C2CP
filter
edge dector
TMRx_CH1
C1DF
C1P/C1CP
filter
edge dector
STIS
External clock
mode A enable
TRGIN
DIV_counter
CK_CNT
CNT_counter
SMSEL=3'b111
ESP
ESDIV
polarity and
edge detector
prescaler
External trigger
Note: The delay between the signal on the input side and the actual clock of the counter is due to the
synchronization circuit.
Figure 14-81 Counting in external clock mode A, with PR=0x32 and DIV=0x0
30
COUNTER
OVFIF
TMR_CLK
110
STIS[2:0]
Clear
CNT_CLK
C2IRAW
000
C2IF[2:0]
31
32
0
1
2
3
4
Figure 14-92 Block diagram of external clock mode B
External clock mode B
enable
TMRx_EXT
ESF
filter
EXT
DIV_counter
CK_CNT
CNT_counter
ECMBEN=1
ESP
ESDIV
polarity and
edge detector
prescaler
Note: The delay between the EXT signal on the input side and the actual clock of the counter is due to
the synchronization circuit.